E. Van Besien

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

E. Beyne, H. Dekkers, E. Van Besien, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

G. Beyer, E. Sleeckx, H. Dekkers, 2010, 2010 IEEE International Interconnect Technology Conference.

Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography

S. Demuynck, E. Van Besien, L. Zhang, 2012, 2012 IEEE International Interconnect Technology Conference.

Fundamental study of atomic layer deposition in and on porous low-k films

E. Van Besien, J. Swerts, P. Verdonck, 2011, 2011 IEEE International Interconnect Technology Conference.

Epitaxial diamond-hexagonal silicon nano-ribbon growth on (001) silicon

E. Van Besien, O. Richard, H. Bender, 2015, Scientific Reports.