J. Geypen

发表

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

K. Wostyn, J. Geypen, H. Bender, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2021, 2021 Symposium on VLSI Technology.

Selective Epitaxial Growth of Germanium on Si Wafers with Shallow Trench Isolation: An Approach for Ge Virtual Substrates

G. Wang, J. Geypen, H. Bender, 2008 .

Stuffing-enabled surface confinement of silanes used as sealing agents on CF4 plasma-exposed 2.0 p-OSG films

J. Geypen, H. Bender, C. Detavernier, 2015 .

Impact of the chemical concentration on the solid-phase epitaxial regrowth of phosphorus implanted preamorphized germanium

O. Richard, J. Geypen, A. Satta, 2009 .

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

S. Chew, T. Schram, K. Devriendt, 2013 .

Process control & integration options of RMG technology for aggressively scaled devices

S. Chew, T. Schram, K. Devriendt, 2012, Symposium on VLSI Technology.

W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

Tom Schram, Anabela Veloso, S. A. Chew, 2013 .

Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity

A. Hikavyy, E. Rosseel, O. Richard, 2007, 2007 15th International Conference on Advanced Thermal Processing of Semiconductors.

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

D. Mocuta, J. Mitard, F. Masuoka, 2019, 2019 Symposium on VLSI Technology.

Study of ohmic contacts to n-type Ge: Snowplow and laser activation

E. Rosseel, J. Geypen, H. Bender, 2011 .

Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 103s retention, >1011 cycles endurance and Lg scalability down to 14nm

D. Tsvetanova, H. Dekkers, A. Chasin, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

Buried Power Rail Metal exploration towards the 1 nm Node

H. Mertens, K. Devriendt, J. Geypen, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2022, 2022 International Electron Devices Meeting (IEDM).

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

E. Simoen, G. Hellings, E. Vecchio, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Structural characterization of through silicon vias

J. Geypen, H. Philipsen, A. Radisic, 2012, Journal of Materials Science.

The influence of post-etch InGaAs fin profile on electrical performance

M. A. Pourghaderi, J. Geypen, H. Bender, 2013 .