K. Barla

发表

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Nucleation Behavior of III/V Crystal Selectively Grown Inside Nano-Scale Trenches: The Influence of Trench Width

K. Barla, A. Thean, N. Collaert, 2015 .

Heteroepitaxy of InP on Si(001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering

K. Barla, A. Thean, N. Collaert, 2014 .

Replacement fin processing for III–V on Si: From FinFets to nanowires

Niamh Waldron, Nadine Collaert, Farid Sebaai, 2016 .

Layer-controlled epitaxy of 2D semiconductors: bridging nanoscale phenomena to wafer-scale uniformity

K. Barla, G. Pourtois, I. Radu, 2018, Nanotechnology.

Ultimate nano-electronics

Jerome Mitard, Rita Rooyackers, Anne Vandooren, 2015 .

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, IEEE Transactions on Electron Devices.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Selective metal-organic chemical vapor deposition growth of high quality GaAs on Si(001)

Niamh Waldron, Aaron Thean, Wilfried Vandervorst, 2014 .

Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

Aaron Thean, Jacopo Franco, Stefan De Gendt, 2014 .

The kinetics and mechanism of oxide layer formation from porous silicon formed on p‐Si substrates

K. Barla, K. Barla, G. Bomchil, 1987 .

The fabrication of TiN films by reactive evaporation and rapid thermal annealing

K. Barla, L. Dignard-Bailey, J. Currie, 1988 .

Defect engineering for shallow n‐type junctions in germanium: Facts and fiction

K. Barla, N. Collaert, E. Simoen, 2016 .

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

K. Barla, A. Thean, L. Witters, 2016 .

Oscillatory behavior of the tunneling current in ultra thin gate dielectrics: Influence of various physical and technological parameters☆

Gerard Ghibaudo, K. Barla, G. Ghibaudo, 1997 .

Integration of Fluorine-doped Silicon oxide in copper pilot line for 0.12-µm technology

K. Barla, J. Michailos, C. Chaton, 2002 .

Tensile Contact Etch Stop Nitride for nMOS Performance Enhancement: Influence of the Film Morphology

K. Barla, F. Arnaud, C. Ortolland, 2006 .

Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Contact resistivities of metal-insulator-semiconductor contacts and metal-semiconductor contacts

K. Barla, N. Horiguchi, A. Thean, 2016 .

Silicon Surface Chemical Treatments in Oxide/Nitride Dielectric Stack Properties

K. Barla, J. Regolini, S. Petitdidier, 2002 .

Managing annealing pattern effects in 45nm low power CMOS technology

K. Barla, R. Beneyton, C. Gallon, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Origin of local temperature variation during spike anneal and millisecond anneal

K. Barla, R. Beneyton, M. Bidaud, 2008, 2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors.

Low-Resistance Titanium Contacts and Thermally Unstable Nickel Germanide Contacts on p-Type Germanium

T. Schram, K. Barla, N. Horiguchi, 2016, IEEE Electron Device Letters.

High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

A. Hikavyy, A. De Keersgieter, G. Mannaert, 2019, 2019 Symposium on VLSI Technology.

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, 2018 IEEE Symposium on VLSI Technology.

A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Determination of lattice parameter and elastic properties of porous silicon by X-ray diffraction

K. Barla, A. Freund, K. Barla, 1984 .

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact

Naoto Horiguchi, Tom Schram, Nadine Collaert, 2016, IEEE Transactions on Electron Devices.

Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2

Naoto Horiguchi, Nadine Collaert, Daeyong Kim, 2016, IEEE Transactions on Electron Devices.

Low temperature deposition of 2D WS2 layers from WF6 and H2S precursors: impact of reducing agents.

S. De Gendt, S. Van Elshocht, H. Bender, 2015, Chemical communications.

Porosity and Pore Size Distributions of Porous Silicon Layers

K. Barla, K. Barla, G. Bomchil, 1987 .

Stress in oxidized porous silicon layers

K. Barla, G. Bomchil, R. Hérino, 1986 .

Pore Size Distribution in Porous Silicon Studied by Adsorption Isotherms

K. Barla, G. Bomchil, J. Pfister, 1983 .

Microstructure of Porous silicon and its evolution with temperature

K. Barla, K. Barla, G. Bomchil, 1984 .

Quantitative Auger sputter depth profiling of very thin nitrided oxide

R. Pantel, K. Barla, A. Straboni, 1990 .

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Demonstration of Direction Dependent Conduction through MoS2 Films Prepared by Tunable Mass Transport Fabrication

K. Barla, I. Radu, M. Caymax, 2016 .

Plasma nitrided oxide films as a thin gate dielectric

K. Barla, A. Straboni, K. Barla, 1989 .

EUV patterning using CAR or MOX photoresist at low dose exposure for sub 36nm pitch

Akiteru Ko, Peter Biolsi, Danilo De Simone, 2018, Advanced Lithography.

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

Naoto Horiguchi, Aaron Thean, Tom Schram, 2014, IEEE Electron Device Letters.

1.5×10−9 Ωcm2 Contact resistivity on highly doped Si:P using Ge pre-amorphization and Ti silicidation

E. Rosseel, S. Demuynck, K. Barla, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond

S. Demuynck, K. Barla, N. Horiguchi, 2016, 2016 16th International Workshop on Junction Technology (IWJT).

Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

E. Rosseel, T. Schram, S. Demuynck, 2015, IEEE Electron Device Letters.

Process options to enable (sub-)1e-9 Ohm.cm2 contact resistivity on Si devices

S. Chew, E. Rosseel, S. Demuynck, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE Symposium on VLSI Technology.

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

X-ray topographic characterization of porous silicon layers

K. Barla, J. Baruchel, K. Barla, 1984 .

Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology

F. S. Johnson, R. Wachnik, K. Barla, 2011 .

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of III-V on Si: What About Defect Density?

Niamh Waldron, Aaron Thean, Wilfried Vandervorst, 2014 .

III/V nano ridge structures for optical applications on patterned 300 mm silicon substrate

Bin Tian, Robert Langer, Kathy Barla, 2016 .

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

Niamh Waldron, Nadine Collaert, Farid Sebaai, 2014, IEEE Electron Device Letters.

Study of electrically active defects in epitaxial layers on silicon

A. Hikavyy, K. Barla, R. Loo, 2016, 2016 China Semiconductor Technology International Conference (CSTIC).

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

The economic impact of EUV lithography on critical process modules

Geert Vandenberghe, Diederik Verkest, Naoto Horiguchi, 2014, Advanced Lithography.

Exploration of a low-temperature PEALD technology to trim and smooth 193i photoresist

Gian Francesco Lorusso, Vito Rutigliani, Vassilios Constantoudis, 2017, Advanced Lithography.

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

Model for the oxide thickness dependence of SILC generation based on anode hole injection process

K. Barla, G. Ghibaudo, S. Bruyère, 1999 .

Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

C. Merckling, N. Waldron, N. Collaert, 2016, 2016 IEEE Symposium on VLSI Technology.

(Invited) Integration of III/V Hetero-Structures By Selective Area Growth on Si for Nano- and Optoelectronics

Robert Langer, Kathy Barla, Bernardette Kunert, 2016 .

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

A. Vais, C. Merckling, N. Waldron, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

New bending mode in SAQP Si fins and its mitigation

K. Barla, A. Sepúlveda, K. Kenis, 2022, Materials Science in Semiconductor Processing.

Patterning challenges in advanced device architectures: FinFETs to nanowires

L. Witters, N. Waldron, N. Collaert, 2016, SPIE Advanced Lithography.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

H. Mertens, A. Hikavyy, H. Bender, 2014, 2014 IEEE International Electron Devices Meeting.