D. Mocuta

发表

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)

C. Ouyang, D. Mocuta, P. O'Neil, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Adsorption and electron-stimulated dissociation of ammonia on Cu(110): an ESDIAD study

D. Mocuta, J. Yates, J. Ahner, 1997 .

Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions

D. Mocuta, I. Radu, I. Young, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

W. Li, A. Vandooren, Liesbeth Witters, 2018, 2018 International Conference on IC Design & Technology (ICICDT).

Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration

F. Inoue, D. Mocuta, N. Collaert, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

F. M. Bufler, F. Inoue, R. Ritzenthaler, 2018, IEEE Transactions on Electron Devices.

Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory Applications

D. Mocuta, N. Horiguchi, A. Veloso, 2019, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

K. Wostyn, J. Geypen, H. Bender, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Processing Technologies for Advanced Ge Devices

Naoto Horiguchi, Jerome Mitard, Liesbeth Witters, 2017 .

Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

K. Wostyn, H. Dekkers, D. Mocuta, 2019, IEEE Transactions on Electron Devices.

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, IEEE Transactions on Electron Devices.

The impact of the temperature on In0.53Ga0.47As nTFETs

D. Mocuta, N. Collaert, R. Rooyackers, 2018 .

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Invited) Vertical Nanowire FET Integration and Device Aspects

Nadine Collaert, Aaron Thean, Tsvetan Ivanov, 2016 .

Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node

Diederik Verkest, Aaron Thean, Julien Ryckaert, 2015, Advanced Lithography.

Strained Si CMOS (SS CMOS) technology: Opportunities and challenges

Keith A. Jenkins, Byoung Hun Lee, P. Oldiges, 2003 .

Demonstration of 2e12cm2eV1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5nm EOT

Iuliana Radu, J. Van Houdt, D. Lin, 2017 .

Tunneling Transistors Based on MoS2/MoTe2 Van der Waals Heterostructures

Anh Khoa Augustin Lu, D. Mocuta, I. Radu, 2018, IEEE Journal of the Electron Devices Society.

The Complementary FET (CFET) for CMOS scaling beyond N3

G. Bouche, J. Ryckaert, D. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

Improvement in drain-induced-barrier-lowering and on-state current characteristics of bulk Si fin field-effect-transistors using high temperature Phosphorus extension ion implantation

G. Mannaert, D. Mocuta, N. Horiguchi, 2019, Solid-State Electronics.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?

D. Mocuta, K. Kinoshita, T. Ishijima, 2018 .

A flexible InGaAs nanomembrane PhotoFET with tunable responsivities in near- and short-wave IR region for lightweight imaging applications

D. Mocuta, A. Thean, N. Collaert, 2019, APL Materials.

An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2018, 2018 IEEE Symposium on VLSI Technology.

RC Benefits of Advanced Metallization Options

Christopher J. Wilson, D. Mocuta, K. Croes, 2019, IEEE Transactions on Electron Devices.

Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Impact of Wire Geometry on Interconnect RC and Circuit Delay

Diederik Verkest, Christopher J. Wilson, Aaron Thean, 2016, IEEE Transactions on Electron Devices.

Modeling of graphene for interconnect applications

D. Mocuta, D. Verkest, B. Sorée, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Oxygen Gettering Cap to Scavenge Parasitic Oxide Interlayer in TiSi Contacts

D. Mocuta, N. Horiguchi, N. Collaert, 2019, IEEE Electron Device Letters.

Low-Frequency Noise Behavior of nMOSFETs with Different Al2O3 Capping Layer Thickness and TiN Gate

B. T. Chan, D. Mocuta, B. Govoreanu, 2019 .

On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials

D. Mocuta, A. Thean, N. Collaert, 2018, Advances in Science, Technology and Engineering Systems Journal.

Tracking the motion of chemisorbed molecules on their adsorption sites.

D. Mocuta, J. Yates, J. Ahner, 1998, Proceedings of the National Academy of Sciences of the United States of America.

High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

A. Hikavyy, A. De Keersgieter, G. Mannaert, 2019, 2019 Symposium on VLSI Technology.

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, 2018 IEEE Symposium on VLSI Technology.

A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

TiSi(Ge) Contacts Formed at Low Temperature Achieving Around $2 \,\, \times \,\, 10^{-{9}}~\Omega $ cm2 Contact Resistivities to p-SiGe

D. Mocuta, N. Horiguchi, N. Collaert, 2017, IEEE Transactions on Electron Devices.

Spin-torque-driven MTJs with extended free layer for logic applications

D. Mocuta, I. Radu, J. Swerts, 2018, Journal of Physics D: Applied Physics.

Instant-On Spin Torque in Noncollinear Magnetic Tunnel Junctions

Christopher J. Wilson, D. Mocuta, I. Radu, 2018, Physical Review Applied.

Fabrication of magnetic tunnel junctions connected through a continuous free layer to enable spin logic devices

Christopher J. Wilson, D. Mocuta, I. Radu, 2017, 1711.03609.

Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

H. Mertens, R. Ritzenthaler, M. Kim, 2018, International Electron Devices Meeting.

Self-organized nanostructures: an ESDIAD study of the striped oxidized Cu(110) surface

D. Mocuta, J. Yates, J. Ahner, 1999 .

Dynamics of the striped nanostructure of the oxidized Cu(110) surface: A momentum-resolved electron stimulated desorption ion angular distribution study

D. Mocuta, J. Yates, J. Ahner, 1999 .

Titanium (germano-)silicides featuring 10−9 Ω·cm2 contact resistivity and improved compatibility to advanced CMOS technology

S. Chew, D. Mocuta, N. Horiguchi, 2018, 2018 18th International Workshop on Junction Technology (IWJT).

Momentum resolved electron stimulated desorption ion angular distribution, a new technique, probing the low frequency motion of adsorbed molecules on single crystal surfaces

D. Mocuta, J. Yates, J. Ahner, 1999 .

Adsorption at copper oxide island edges

D. Mocuta, J. Yates, J. Ahner, 2000 .

Thermal excitation of rotation of the methyl group in chemisorbed acetate on Cu(110)

D. Mocuta, J. Yates, J. Ahner, 2000 .

The frustrated translational mode of CO on Cu(110): Azimuthal anisotropy studied by helium atom scattering—A comparison with time-of-flight electron stimulated desorption of ion angular distribution measurements

D. Mocuta, J. Yates, C. Wöll, 1998 .

Trapping a precursor to chemisorption at 32 K—NH3 adsorption on Cu(110)

D. Mocuta, J. Yates, J. Ahner, 1997 .

MEASUREMENT OF ANISOTROPY IN THE LATERAL MOMENTUM OF A VIBRATING ADSORBED MOLECULE : CO/CU(110)

R. D. Ramsier, D. Mocuta, J. Yates, 1997 .

Momentum-resolved excited-electron lifetimes on stepped Cu(7 7 5)

D. Mocuta, R. Osgood, S. Smadici, 2002 .

TOF-ESDIAD measurements of a coadsorbate system: CO on an oxidized Cu(110) surface

D. Mocuta, J. Yates, J. Ahner, 1997 .

Kinetic energy distributions and momentum resolved ESDIAD measurements of CO + ions and excited neutral CO∗ molecules — {CO}/{Cu(110) }

D. Mocuta, J. Yates, J. Ahner, 1997 .

Adsorbate–adsorbate repulsions—the coverage dependence of the adsorption structure of CO on Cu(110) as studied by electron‐stimulated desorption ion angular distribution

R. D. Ramsier, D. Mocuta, J. Yates, 1996 .

Lateral motion of image-state electrons for metal-adsorbate regions on stepped metal substrates

D. Mocuta, R. Osgood, S. Smadici, 2004 .

Observation of a one-dimensional state on stepped Cu(775)

D. Mocuta, R. Osgood, S. Smadici, 2001 .

Epitaxial diamond-hexagonal silicon nano-ribbon growth on (001) silicon

E. Van Besien, O. Richard, H. Bender, 2015, Scientific Reports.

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

D. Mocuta, J. Mitard, F. Masuoka, 2019, 2019 Symposium on VLSI Technology.

Dynamical studies of surface species — observing librational motions of adsorbates

R. D. Ramsier, D. Mocuta, J. Yates, 1997 .

Lanthanum and Lanthanum Silicide Contacts on N-Type Silicon

Naoto Horiguchi, Yu-Long Jiang, Nadine Collaert, 2017, IEEE Electron Device Letters.

Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

D. Mocuta, N. Horiguchi, A. Veloso, 2020, Solid-State Electronics.

Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal

A. Hikavyy, S. Chew, G. Mannaert, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

J. Ryckaert, D. Verkest, M. Badaroglu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Thermal Stability of TiN/Ti/p+-Si0.3Ge0.7 Contact With Ultralow Contact Resistivity

D. Mocuta, N. Horiguchi, N. Collaert, 2018, IEEE Electron Device Letters.

Replacement Metal Contact Using Sacrificial ILD0 for Wrap Around Contact in Scaled FinFET Technology

S. Chew, K. Devriendt, S. Demuynck, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Interconnected magnetic tunnel junctions for spin-logic applications

Iuliana Radu, Morin Dehan, Odysseas Zografos, 2018 .

The impact of sequential-3D integration on semiconductor scaling roadmap

B. Parvais, A. Vandooren, J. Ryckaert, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Improved Ohmic Performance by the Metallic Bilayer Contact Stack of Oxygen-Incorporated La/Ultrathin TiSix on n-Si

Naoto Horiguchi, Yu-Long Jiang, Nadine Collaert, 2018, IEEE Transactions on Electron Devices.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Junctionless versus inversion-mode lateral semiconductor nanowire transistors

B Kaczer, H. Mertens, D. Mocuta, 2018, Journal of physics. Condensed matter : an Institute of Physics journal.

Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

B. Douhard, O. Richard, D. Mocuta, 2018 .

Wide operating window spin-torque majority gate towards large-scale integration of logic circuits

Iuliana Radu, Odysseas Zografos, Adrien Vaysset, 2018 .

Vertical nanowire FET integration and device aspects

B. T. Chan, Z. Tao, E. Rosseel, 2016 .

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures

Iuliana Radu, Guido Groeseneken, Cedric Huyghebaert, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation

K. Wostyn, D. Mocuta, N. Horiguchi, 2019, 2019 Symposium on VLSI Technology.

Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues

Fen Chen, M. Shinosky, Yanfeng Wang, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Modeling of Via Resistance for Advanced Technology Nodes

Christopher J. Wilson, Weimin Gao, Ivan Ciofi, 2017, IEEE Transactions on Electron Devices.

Towards high performance sub-10nm finW bulk FinFET technology

Naoto Horiguchi, Jérôme Mitard, P. Eyben, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Holisitic device exploration for 7nm node

Diederik Verkest, Naoto Horiguchi, Aaron Thean, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs

Nadine Collaert, Tsvetan Ivanov, Dennis Lin, 2018, 2018 IEEE Symposium on VLSI Technology.

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

D. Mocuta, A. Thean, N. Collaert, 2016 .

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Geert Hellings, Eddy Simoen, Niamh Waldron, 2017 .

Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET

A. Hikavyy, A. De Keersgieter, H. Bender, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

Z. Tao, K. Devriendt, D. Mocuta, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Tunnel FETs for low power electronics

D. Mocuta, N. Collaert, N. Waldron, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).