A. Veloso

发表

Vertical devices for future nano-electronic applications

A. Thean, N. Collaert, A. Veloso, 2016 .

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

O. Richard, H. Bender, N. Collaert, 2008, 2008 Symposium on VLSI Technology.

Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

O. Richard, H. Bender, N. Collaert, 2008, 2008 IEEE International SOI Conference.

High performance Si.45Ge.55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation

A. Hikavyy, H. Bender, N. Horiguchi, 2011, 2011 International Electron Devices Meeting.

Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

T. Schram, A. Veloso, M. Jurczak, 2008, 2008 Symposium on VLSI Technology.

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

A. Hikavyy, G. Mannaert, T. Schram, 2011, 2011 International Electron Devices Meeting.

Review of FINFET technology

N. Collaert, A. Veloso, S. Biesemans, 2009, 2009 IEEE International SOI Conference.

FinFETs and Their Futures

N. Horiguchi, N. Collaert, A. Veloso, 2011 .

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

A. Hikavyy, K. Devriendt, S. Demuynck, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

S. Chew, T. Schram, K. Devriendt, 2014 .

Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

A. Veloso, T. Grasser, B. Kaczer, 2011 .

Benchmarking time-dependent variability of junctionless nanowire FETs

B. Kaczer, T. Grasser, G. Hellings, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs

H. Mertens, R. Ritzenthaler, N. Horiguchi, 2021 .

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

H. Mertens, R. Ritzenthaler, N. Horiguchi, 2020, 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs

A. Veloso, B. Parvais, A. Dixit, 2019, IEEE Transactions on Electron Devices.

Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory Applications

D. Mocuta, N. Horiguchi, A. Veloso, 2019, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Junctionless Versus Inversion-Mode Gate-All-Around Nanowire Transistors From a Low-Frequency Noise Perspective

N. Collaert, A. Veloso, P. Matagne, 2018, IEEE Transactions on Electron Devices.

Significant reduction of Positive Bias Temperature Instability in high-k/metal-gate nFETs by incorporation of rare earth metals

Anabela Veloso, Guido Groeseneken, Ben Kaczer, 2009 .

Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization

S. Chew, T. Schram, A. Veloso, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Ultimate nano-electronics

Jerome Mitard, Rita Rooyackers, Anne Vandooren, 2015 .

Stress simulations for optimal mobility group IV p- and nMOS FinFETs for the 14 nm node and beyond

A. Hikavyy, A. De Keersgieter, O. Richard, 2012, 2012 International Electron Devices Meeting.

1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor

R. Ritzenthaler, N. Horiguchi, A. Thean, 2013 .

Weibull slope and voltage acceleration of ultra-thin (1.1-1.45 nm EOT) oxynitrides

Anabela Veloso, Guido Groeseneken, Ben Kaczer, 2004 .

Invited) Vertical Nanowire FET Integration and Device Aspects

Nadine Collaert, Aaron Thean, Tsvetan Ivanov, 2016 .

The Complementary FET (CFET) for CMOS scaling beyond N3

G. Bouche, J. Ryckaert, D. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

N. Horiguchi, N. Collaert, A. Veloso, 2018 .

On the Oxide Trap Density and Profiles of 1-nm EOT Metal-Gate Last CMOS Transistors Assessed by Low-Frequency Noise

N. Horiguchi, A. Veloso, E. Simoen, 2013, IEEE Transactions on Electron Devices.

Sidewall crystalline orientation effect of post-treatments for a replacement metal gate bulk fin field effect transistor.

N. Horiguchi, A. Thean, A. Veloso, 2013, ACS applied materials & interfaces.

Assessment of DC and low-frequency noise performances of triple-gate FinFETs at cryogenic temperatures

N. Collaert, A. Veloso, E. Simoen, 2016 .

Technology development challenges for advanced group IV semiconductor devices

A. Thean, N. Collaert, A. Veloso, 2016 .

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON

A. Veloso, K. Opsomer, M. Jurczak, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

On trap identification in triple-gate FinFETs and Gate-All-Around nanowire MOSFETs using low frequency noise spectroscopy

N. Collaert, A. Veloso, E. Simoen, 2017, 2017 International Conference on Noise and Fluctuations (ICNF).

Si GAA NW FETs Threshold Voltage Evaluation

A. Veloso, E. Simoen, B. Crețu, 2022, Solid-State Electronics.

Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOSFET down to -100 oC

A. Veloso, P. Agopian, E. Simoen, 2022, Journal of Integrated Circuits and Systems.

Size Independent pH Sensitivity for Ion Sensitive FinFETs Down to 10 nm Width

Z. Tao, A. Veloso, L. Lagae, 2019, IEEE Sensors Journal.

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-κ/Metal-Gate pMOSFETs

N. Horiguchi, A. Veloso, V. Paraschiv, 2014 .

Further optimization of plasma nitridation of ultra-thin oxides for 65nm node MOSFETs

A. Veloso, F. Nouri, K. Ahmed, 2004 .

Low-Frequency Noise Assessment of Vertically Stacked Si n-Channel Nanosheet FETs With Different Metal Gates

N. Horiguchi, A. Veloso, E. Simoen, 2020, IEEE Transactions on Electron Devices.

Low-frequency noise measurements at liquid helium temperature operation in ultra-thin buried oxide transistors – Physical interpretation of transport phenomena

A. Veloso, E. Simoen, O. Touayar, 2018, Solid-State Electronics.

Low Frequency Noise Analysis for Post-Treatment of Replacement Metal Gate

N. Horiguchi, A. Thean, A. Veloso, 2013, IEEE Transactions on Electron Devices.

Impact of oxide trap passivation by fluorine on the low-frequency noise behavior of gate-last pMOSFETs

N. Horiguchi, A. Veloso, V. Paraschiv, 2013, 2013 22nd International Conference on Noise and Fluctuations (ICNF).

PVD-HfSiON gate dielectrics with Ni-FUSI electrode for 65nm LSTP application

A. Veloso, M. Jurczak, S. Kubicek, 2005 .

Development of a Wet Silicon Removal Process for Replacement Metal Gate and Sacrificial Fin

A. Veloso, F. Sebaai, H. Struyf, 2011 .

Insights in low frequency noise of advanced and high-mobility channel transistors

A. Veloso, M. Jurczak, P. Fazan, 2012, 2012 International Electron Devices Meeting.

Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications

Carlos H. S. Coelho, A. Veloso, P. Agopian, 2022, Journal of Integrated Circuits and Systems.

Impact of the Channel Doping on the Low-Frequency Noise of Silicon Vertical Nanowire pFETs

A. Veloso, P. Matagne, E. Simoen, 2022, Solid-State Electronics.

On the Asymmetry of the DC and Low-Frequency Noise Characteristics of Vertical Nanowire MOSFETs with Bulk Source Contact

A. Veloso, P. Matagne, E. Simoen, 2022, Solid-State Electronics.

Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

A. Hikavyy, E. Rosseel, K. Devriendt, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices

Carlos H. S. Coelho, A. Veloso, P. Agopian, 2021, 2021 IEEE Latin America Electron Devices Conference (LAEDC).

The impact of gate length scaling on UTBOX FDSOI devices: The digital/analog performance of extension-less structures

A. Veloso, M. Jurczak, M. Aoulaiche, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

Improved physics-based analysis to discriminate the flicker noise origin at very low temperature and drain voltage polarization

N. Collaert, A. Veloso, E. Simoen, 2020 .

Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology

A. Thean, N. Collaert, A. Veloso, 2017 .

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

S. Chew, T. Schram, K. Devriendt, 2013 .

Process control & integration options of RMG technology for aggressively scaled devices

S. Chew, T. Schram, K. Devriendt, 2012, Symposium on VLSI Technology.

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

C. Vrancken, A. Veloso, S. Biesemans, 2006, IEEE Electron Device Letters.

W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

Tom Schram, Anabela Veloso, S. A. Chew, 2013 .

ESD performance of high mobility SiGe quantum well bulk finFET diodes and PMOS devices

Mirko Scholz, Dimitri Linten, Geert Hellings, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Low frequency noise performance of gate-first and replacement metal gate CMOS technologies

N. Horiguchi, A. Veloso, V. Paraschiv, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

Low-Frequency Noise Assessment of the Oxide Quality of Gate-Last High- $k$ pMOSFETs

E. Simoen, C. Claeys, N. Horiguchi, 2012, IEEE Electron Device Letters.

Ni fully silicided gates for 45nm CMOS applications

T. Schram, A. Veloso, G. Pourtois, 2005 .

Silicides — Recent Advances and Prospects

A. Veloso, G. Pourtois, J. Kittl, 2005 .

Beyond-Si materials and devices for more Moore and more than Moore applications

A. Vandooren, Anabela Veloso, Liesbeth Witters, 2016, 2016 International Conference on IC Design and Technology (ICICDT).

Advances on doping strategies for triple-gate finFETs and lateral gate-all-around nanowire FETs and their impact on device performance

Naoto Horiguchi, Anabela Veloso, Nadine Collaert, 2017 .

Top-down InGaAs nanowire and fin vertical FETs with record performance

H. Bender, A. Thean, N. Collaert, 2016, 2016 IEEE Symposium on VLSI Technology.

Time Evolution of DIBL in Gate-All-Around Nanowire MOSFETs During Hot-Carrier Stress

A. Veloso, B. Parvais, A. Dixit, 2021, IEEE Transactions on Electron Devices.

The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices

A. Vandooren, R. Rooyackers, E. Simoen, 2015, 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro).

Challenges with Respect to High-k/Metal Gate Stack Etching and Cleaning

T. Schram, A. Veloso, S. Kubicek, 2007 .

(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling

A. Jourdain, A. De Keersgieter, N. Horiguchi, 2022, ECS Meeting Abstracts.

Vertical GAAFETs for the Ultimate CMOS Scaling

Diederik Verkest, Anabela Veloso, Praveen Raghavan, 2015, IEEE Transactions on Electron Devices.

Stress Techniques and Mobility Enhancement in FinFET Architectures

Naoto Horiguchi, Geert Hellings, Anabela Veloso, 2013 .

Low–Frequency Noise in Vertically Stacked Si n–Channel Nanosheet FETs

N. Horiguchi, A. Veloso, E. Simoen, 2020, IEEE Electron Device Letters.

Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

D. Mocuta, N. Horiguchi, A. Veloso, 2020, Solid-State Electronics.

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

A. Veloso, C. Adelmann, A. Lauwers, 2007, IEEE Electron Device Letters.

Work function of Ni3Si2 on HfSixOy and SiO2 and its implication for Ni fully silicided gate applications

A. Veloso, J. Kittl, B. O’Sullivan, 2007 .

Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates

O. Richard, A. Veloso, M. Jurczak, 2006 .

Silicides for advanced CMOS devices

O. Richard, H. Bender, A. Veloso, 2005 .

Investigation of Ni fully silicided gates for sub-45 nm CMOS technologies

T. Schram, A. Veloso, J. Kittl, 2004 .

Modulation of the effective work function of fully-silicided (FUSI) gate stacks

A. Veloso, G. Pourtois, J. Kittl, 2007 .

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON

A. Veloso, J. Kittl, A. Lauwers, 2006, IEEE Electron Device Letters.

Linewidth effect and phase control in Ni fully silicided gates

A. Veloso, J. Kittl, A. Lauwers, 2006, IEEE Electron Device Letters.

Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

A. Veloso, J. Kittl, A. Lauwers, 2008, IEEE Electron Device Letters.

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

A. Veloso, J. Kittl, A. Lauwers, 2006, IEEE Electron Device Letters.

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

A. Veloso, M. Jurczak, J. Kittl, 2008, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

A. Veloso, G. Pourtois, M. Jurczak, 2007, IEEE Electron Device Letters.

Achieving low V T Ni-FUSI CMOS via lanthanide incorporation in the gate stack

A. Veloso, M. Jurczak, J. Kittl, 2007 .

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs

K. Devriendt, A. Veloso, M. Jurczak, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

E. Augendre, A. Veloso, S. Biesemans, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Enabling CD SEM metrology for 5nm technology node and beyond

Gian Francesco Lorusso, Naoto Horiguchi, Christopher J. Wilson, 2017, Advanced Lithography.

Trade-off Analysis between gm/ID and fT of nanosheet NMOS Transistors with Different Metal Gate Stack at High Temperature

A. Veloso, P. Agopian, E. Simoen, 2022, Solid-State Electronics.

Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures

A. Veloso, P. Agopian, E. Simoen, 2021, IEEE Transactions on Electron Devices.

Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-VT, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets

H. Mertens, R. Ritzenthaler, M. Kim, 2019, Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials.

Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures

N. Collaert, A. Veloso, E. Simoen, 2018 .

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

A. Veloso, M. Jurczak, A. Lauwers, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Refined DC and Low-Frequency Noise Characterization at Room and Cryogenic Temperatures of Vertically Stacked Silicon Nanosheet FETs

A. Veloso, E. Simoen, B. Crețu, 2023, IEEE Transactions on Electron Devices.

In-depth static and low frequency noise assessment of p-channel gate-all-around vertically stacked silicon nanosheets

A. Veloso, E. Simoen, B. Crețu, 2023, Solid-State Electronics.

Junctionless versus inversion-mode lateral semiconductor nanowire transistors

B Kaczer, H. Mertens, D. Mocuta, 2018, Journal of physics. Condensed matter : an Institute of Physics journal.

Small target compatible dimensional and analytical metrology for semiconductor nanostructures using x-ray fluorescence techniques

A. Hikavyy, A. Veloso, R. Loo, 2023, Advanced Lithography.

Vertical nanowire FET integration and device aspects

B. T. Chan, Z. Tao, E. Rosseel, 2016 .

(Keynote) Gate-All-Around Nanowire & Nanosheet FETs for Advanced, Ultra-Scaled Technologies

H. Mertens, A. Chasin, N. Horiguchi, 2020, ECS Meeting Abstracts.

Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors

Anabela Veloso, Olivier Richard, I. Debusschere, 2007, Microelectron. Reliab..

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

R. Rooyackers, B. Kaczer, S. Locorotondo, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

45nm LSTP FET with FUSI Gate on PVD-HfO2 with excellent drivability by advanced PDA treatment

A. Veloso, M. Jurczak, S. Kubicek, 2005 .

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era

A. Jourdain, N. Horiguchi, A. Veloso, 2021, Electrical Overstress/Electrostatic Discharge Symposium.

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

A. Jourdain, E. Beyne, A. Veloso, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

Middle-of-line plasma dry etch challenges for buried power rail integration

H. Mertens, N. Horiguchi, A. Veloso, 2022, Advanced Lithography.

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node

A. Jourdain, E. Beyne, A. Veloso, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Insights into Scaled Logic Devices Connected from Both Wafer Sides

A. Jourdain, E. Beyne, A. De Keersgieter, 2022, International Electron Devices Meeting.

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

A. Jourdain, E. Beyne, A. Veloso, 2022, International Electron Devices Meeting.

Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs

Jerome Mitard, Anabela Veloso, Guido Groeseneken, 2009 .

On the efficiency of stress techniques in gate-last N-type bulk FinFETs

A. De Keersgieter, N. Collaert, A. Veloso, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

(Invited) Replacement Metal Gate/High-k Last Technology for Aggressively Scaled Planar and FinFET-Based Devices

Naoto Horiguchi, Eddy Simoen, Anabela Veloso, 2014 .

Record performance Top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets

N. Collaert, A. Veloso, T. Ivanov, 2017, International Electron Devices Meeting.

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Geert Hellings, Eddy Simoen, Niamh Waldron, 2017 .

Stress in Silicon–Germanium Nanowires: Layout Dependence and Imperfect Source/Drain Epitaxial Stressors

A. Hikavyy, A. De Keersgieter, N. Horiguchi, 2021, IEEE Transactions on Electron Devices.

(Invited) Stress Simulations of Fins, Wires, and Nanosheets

A. Hikavyy, A. De Keersgieter, N. Horiguchi, 2020, ECS Meeting Abstracts.

Nanosheet-based Device Architectures with Front/Backside Connectivity: Opportunities for S/D Engineering to Enable Advanced CMOS Logic Scaling

A. Hikavyy, N. Horiguchi, A. Veloso, 2023, International Workshop on Junction Technology.

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling

A. Jourdain, A. Hikavyy, N. Horiguchi, 2022, International Conference on IC Design & Technology.

Operational Transconductance Amplifier Design with Gate-All-Around Nanosheet MOSFET using Experimental Lookup Table Approach

A. Veloso, P. Agopian, E. Simoen, 2021, 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS).

Patterning challenges in advanced device architectures: FinFETs to nanowires

L. Witters, N. Waldron, N. Collaert, 2016, SPIE Advanced Lithography.

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

E. Simoen, G. Hellings, E. Vecchio, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Reliability screening of high-k dielectrics based on voltage ramp stress

Anabela Veloso, Guido Groeseneken, Luigi Pantisano, 2007, Microelectron. Reliab..

On and off state hot carrier reliability in junctionless high-K MG gate-all-around nanowires

A. Thean, N. Collaert, A. Veloso, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

E. Simoen, C. Claeys, A. Veloso, 2012, IEEE Electron Device Letters.

Origin of wide retention distribution in 1T Floating Body RAM

G. Groeseneken, E. Simoen, C. Claeys, 2012, 2012 IEEE International SOI Conference (SOI).

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

ESD Protection Diodes in Sub-5nm Gate-All-Around Nanosheet Technologies

H. Mertens, N. Horiguchi, A. Veloso, 2020, 2020 42nd Annual EOS/ESD Symposium (EOS/ESD).

Impact of the Effective Work Function Gate Metal on the Low-Frequency Noise of Gate-All-Around Silicon-on-Insulator NWFETs

A. Thean, N. Collaert, A. Veloso, 2016, IEEE Electron Device Letters.

Sidewall crystalline orientation effect of post-treatments for a replacement metal gate bulk fin field effect transistor.

N. Horiguchi, A. Thean, A. Veloso, 2013, ACS applied materials & interfaces.

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

S. Van Elshocht, P. Lehnen, C. Vrancken, 2007, 2007 IEEE Symposium on VLSI Technology.

Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

H. Tigelaar, T. Chiarella, J. Ramos, 2006, 2006 International Electron Devices Meeting.

Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI

A. Veloso, M. Jurczak, J. Kittl, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

S. Locorotondo, T. Chiarella, C. Vrancken, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

Naoto Horiguchi, Anabela Veloso, S. Locorotondo, 2010 .

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Discussion of the flicker noise origin at very low temperature and polarisation operation

A. Veloso, E. Simoen, C. Claeys, 2019 .