B. Yang

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

B. Yang, K. Buddharaju, S. Teo, 2008, IEEE Electron Device Letters.

On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs

T. Adam, L. Black, R. Pal, 2008, 2008 Symposium on VLSI Technology.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

FinFET performance advantage at 22nm: An AC perspective

B. Yang, W. Haensch, Y. Zhang, 2008, 2008 Symposium on VLSI Technology.

Silicon-Nanowire MOSFETs

B. Yang, K. Buddharaju, S. Teo, 2008 .

CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

S.H.G. Teo, B. Yang, K. Buddharaju, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.