N. Singh

发表

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

B. Yang, K. Buddharaju, S. Teo, 2008, IEEE Electron Device Letters.

Physical mechanisms of endurance degradation in TMO-RRAM

N. Singh, G. Lo, D. Kwong, 2011, 2011 International Electron Devices Meeting.

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

N. Singh, K. Banerjee, R. Gandhi, 2011, IEEE Electron Device Letters.

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

N. Singh, S. Manhas, S. Maheshwaram, 2011, IEEE Electron Device Letters.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

S.C. Rustagi, R. Kumar, N. Balasubramanian, 2006, IEEE Electron Device Letters.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

S.C. Rustagi, N. Balasubramanian, K. Buddharaju, 2008, IEEE Transactions on Electron Devices.

Sub-femto-farad capacitance-voltage characteristics of single channel gate-all-around nano wire transistors for electrical characterization of carrier transport

N. Singh, G. Lo, D. Kwong, 2008, 2008 IEEE International Electron Devices Meeting.

Vertical silicon nano-pillar for non-volatile memory

N. Singh, V. Pott, E. Ng, 2011, 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference.

New degradation mechanisms and reliability performance in tunneling field effect transistors

N. Singh, G. Lo, D. Kwong, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

$\hbox{HfO}_{x}/\hbox{TiO}_{x}/\hbox{HfO}_{x}/ \hbox{TiO}_{x}$ Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity

N. Singh, G. Lo, D. Kwong, 2011, IEEE Electron Device Letters.

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

N. Singh, G. Lo, D. Kwong, 2009, IEEE Electron Device Letters.

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

S.C. Rustagi, S.H.G. Teo, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Nickel Salicided Source/Drain Extensions for Performance Improvement in Ultrascaled (Sub 10 nm) Si-Nanowire Transistors

N. Singh, D. Kwong, D. Chan, 2009, IEEE Electron Device Letters.

Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity

K. Leong, N. Singh, G. Lo, 2011, IEEE Transactions on Electron Devices.

Numerical investigation on the junctionless nanowire FET

A. Gnudi, S. Reggiani, E. Gnani, 2011, Ulis 2011 Ultimate Integration on Silicon.

Germanium Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal–Oxide–Semiconductor-Compatible Process

N. Singh, G. Lo, M. Bosman, 2011, IEEE Transactions on Electron Devices.

Self-Consistent SchrÖdinger–Poisson Simulations on Capacitance–Voltage Characteristics of Silicon Nanowire Gate-All-Around MOS Devices With Experimental Comparisons

N. Singh, G. Lo, D. Kwong, 2009, IEEE Transactions on Electron Devices.

Modeling of stress-retarded orientation-dependent oxidation: shape engineering of silicon nanowire channels

N. Singh, G. Lo, D. Kwong, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Impact of Gate Electrodes on $\hbox{1}/f$ Noise of Gate-All-Around Silicon Nanowire Transistors

Yong-Zhong Xiong, Xing Zhou, S.C. Rustagi, 2009, IEEE Electron Device Letters.

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region

Yong-Zhong Xiong, Xing Zhou, S.C. Rustagi, 2009, IEEE Electron Device Letters.

Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors

Guo-Qiang Lo, Jianwei Peng, S. J. Lee, 2008 .

Silicon-Nanowire MOSFETs

B. Yang, K. Buddharaju, S. Teo, 2008 .

CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

S.H.G. Teo, B. Yang, K. Buddharaju, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- $\kappa$/Metal-Gate Device Structures

S.C. Rustagi, S.H.G. Teo, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

S.C. Rustagi, S.H.G. Teo, N. Balasubramanian, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Low-Temperature Transport Characteristics and Quantum-Confinement Effects in Gate-All-Around Si-Nanowire N-MOSFET

S.C. Rustagi, N. Balasubramanian, N. Singh, 2007, IEEE Electron Device Letters.

Dual Nanowire PMOSFET with Thin Si Bridge and TaN Gate

N. Singh, G. Lo, W. Goh, 2006, 2006 Conference on Optoelectronic and Microelectronic Materials and Devices.

Junctionless CMOS Transistors with Independent Double Gates

N. Singh, G. Lo, Z. Chen, 2013 .

Low Frequency Noise Behavior of Independent Gate Junctionless FinFET

N. Singh, G. Lo, Zhixian Chen, 2013 .

A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs

S. H. Rasouli, N. Singh, C. Xu, 2011, IEEE Electron Device Letters.

KrF Lithography for Si based 2D honey comb lattice pillars

N. Singh, S. S. Mehta, B. Murthy, 2006, 2006 IEEE Conference on Emerging Technologies - Nanoelectronics.

Performance analysis of nonvolatile gate-all-around charge-trapping TAHOS memory cells

N. Singh, G. Lo, D. Kwong, 2009, 2009 International Semiconductor Device Research Symposium.

Silicon Nanowire Arrays for Ultrasensitive Label-Free Detection of DNA

K. Buddharaju, N. Singh, C. Tung, 2007, TRANSDUCERS 2007 - 2007 International Solid-State Sensors, Actuators and Microsystems Conference.

Integration of High-$\kappa$ Dielectrics and Metal Gate on Gate-All-Around Si-Nanowire-Based Architecture for High-Speed Nonvolatile Charge-Trapping Memory

N. Singh, G. Lo, D. Kwong, 2009, IEEE Electron Device Letters.

Vertical Nanowall Array Covered Silicon Solar Cells

N. Singh, G. Lo, D. Kwong, 2012 .

Simulation and analysis of ZnO- based extended-gate gate-stack junctionless NWFET for hydrogen gas detection

N. Singh, D. Mandal, R. Kar, 2021, Applied Physics A.

Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique

S. Balakumar, N. Singh, G. Lo, 2008, IEEE Electron Device Letters.

Highly compact 1T-1R architecture (4F2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation

X. Li, B. Gao, A. Kamath, 2012, 2012 International Electron Devices Meeting.

Improved Vertical Silicon Nanowire Based Thermoelectric Power Generator With Polyimide Filling

Yida Li, B. C. Tinh, K. Buddharaju, 2012, IEEE Electron Device Letters.

Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

K. Buddharaju, N. Singh, G. Lo, 2011, IEEE Electron Device Letters.

Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

Zhixian Chen, Sungjoo Lee, K Banerjee, 2011, IEEE Electron Device Letters.

Realization of Ni Fully Silicided Gate on Vertical Silicon Nanowire MOSFETs for Adjusting Threshold Voltage $({V}_{T})$

N. Singh, G. Lo, D. Kwong, 2011, IEEE Electron Device Letters.

Silicon Nanowire for Thermoelectric Applications: Effects of Contact Resistance

K. Buddharaju, N. Singh, G. Lo, 2011 .

Boosting Short-Circuit Current With Rationally Designed Periodic Si Nanopillar Surface Texturing for Solar Cells

N. Singh, D. Kwong, X. W. Sun, 2011, IEEE Transactions on Electron Devices.

Boosting short circuit current with rationally designed periodic Si nanopillar surface texturing for thin film solar cell

N. Singh, D. Kwong, H. Yu, 2010, 2010 International Electron Devices Meeting.

Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design

K. Endo, J. F. Chen, S. H. Rasouli, 2011, IEEE Transactions on Electron Devices.

P-i-n junction in silicon nanowires

Rusli, K. Buddharaju, N. Singh, 2008, 2008 2nd IEEE International Nanoelectronics Conference.

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

S.C. Rustagi, N. Balasubramanian, N. Singh, 2006, 2006 International Electron Devices Meeting.

Barrier layer thickness analysis for reliable copper plug process in CMOS technology

S. K. Manhas, G. Q. Lo, N. Singh, 2011, Microelectron. Reliab..

Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique

N. Singh, G. Lo, D. Kwong, 2009, IEEE Electron Device Letters.

Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs

N. Singh, G. Lo, D. Kwong, 2006, 2006 International Electron Devices Meeting.

Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits

N. Singh, S. Manhas, S. Maheshwaram, 2019, IEEE Transactions on Device and Materials Reliability.

Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic

B. Anand, S. Dasgupta, S. K. Manhas, 2012, IEEE Transactions on Nanotechnology.

Nickel-Silicided Schottky Junction CMOS Transistors With Gate-All-Around Nanowire Channels

N. Singh, G. Lo, D. Chi, 2008, IEEE Electron Device Letters.

Effect of nickel silicide induced dopant segregation on vertical silicon nanowire diode performance

K. Leong, N. Singh, G. Lo, 2012 .

Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

N. Singh, G. Lo, K. Pey, 2009, IEEE Electron Device Letters.

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

S.C. Rustagi, N. Balasubramanian, N. Singh, 2007, IEEE Electron Device Letters.

Demonstration of Schottky Barrier NMOS Transistors With Erbium Silicided Source/Drain and Silicon Nanowire Channel

Pooi See Lee, N. Singh, G. Lo, 2008, IEEE Electron Device Letters.

Gate-All-Around Junctionless Nanowire MOSFET With Improved Low-Frequency Noise Behavior

Jianmin Miao, Dim-Lee Kwong, Woo-Tae Park, 2011, IEEE Electron Device Letters.

Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire

Guo-Qiang Lo, Dim-Lee Kwong, Nansheng Shen, 2011, IEEE Electron Device Letters.

Effect of Interface Traps and Oxide Charge on Drain Current Degradation in Tunneling Field-Effect Transistors

Ming-Fu Li, N. Singh, G. Lo, 2010, IEEE Electron Device Letters.

Experimental Studies of Reliability Issues in Tunneling Field-Effect Transistors

N. Singh, G. Lo, D. Kwong, 2010, IEEE Electron Device Letters.

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

Dim-Lee Kwong, N. Singh, W. Maly, 2012, IEEE Electron Device Letters.

CMOS compatible Ge/Si core/shell nanowire gate-all-around pMOSFET integrated with HfO2/TaN gate stack

N. Singh, G. Lo, D. Kwong, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Si Nanopillar Array Surface-Textured Thin-Film Solar Cell With Radial p-n Junction

N. Singh, D. Kwong, P. Lo, 2011, IEEE Electron Device Letters.

Silicon vertical-nano-wire based photovaltaic device

N. Singh, G. Lo, J. Wang, 2010, 2010 Conference Proceedings IPEC.

A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor

N. Singh, K. Banerjee, D. Sarkar, 2010, IEEE Electron Device Letters.

Gate Tunneling in Nanowire MOSFETs

N. Singh, G. Lo, D. Kwong, 2011, IEEE Electron Device Letters.

Silicon nanowires thermoelectric devices

K. Buddharaju, N. Singh, G. Lo, 2010, 2010 Conference Proceedings IPEC.

Evaluation of a silicon nanowire based thermoelectric cooler performance through contact processes considerations

K. Buddharaju, N. Singh, Sungjoo Lee, 2012 .

High-Performance Poly-Si Vertical Nanowire Thin-Film Transistor and the Inverter Demonstration

N. Singh, G. Lo, D. Kwong, 2011, IEEE Electron Device Letters.

Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body

D.S.H. Chan, N. Balasubramanian, N. Singh, 2006, IEEE Electron Device Letters.

Germanium-Rich SiGe Nanowires Formed Through Oxidation of Patterned SiGe FINs on Insulator

S. Balakumar, K. Buddharaju, N. Singh, 2009 .

Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application

K. Leong, N. Singh, G. Lo, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application

K. Leong, N. Singh, G. Lo, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

M. Marek-Sadowska, W. Maly, N. Singh, 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.

A novel low aspect-ratio Si nano-hemisphere surface texturing scheme for ultrathin film solar cells

N. Singh, D. Kwong, H. Yu, 2011, 2011 International Electron Devices Meeting.

Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φm and VT tune-ability

N. Singh, G. Lo, D. Kwong, 2008, 2008 IEEE International Electron Devices Meeting.

Multibit Programmable Flash Memory Realized on Vertical Si Nanowire Channel

N. Singh, G. Lo, D. Kwong, 2010, IEEE Electron Device Letters.