P. Kapur

发表

A Low-Power, Highly Scalable, Vertical Double-Gate MOSFET Using Novel Processes

Hoon Cho, P. Kapur, P. Kalavade, 2007, IEEE Transactions on Electron Devices.

Optical interconnects for future high performance integrated circuits

P. Kapur, K. Saraswat, 2003 .

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

P. Kapur, K. Saraswat, Kyung-Hoae Koo, 2007, IEEE Transactions on Electron Devices.

Comparisons between electrical and optical interconnects for on-chip signaling

P. Kapur, K. Saraswat, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Performance Comparison between capacitively driven low swing and conventional interconnects for CU and carbon nanotube wire technologies

P. Kapur, K. Saraswat, Kyung-Hoae Koo, 2009, 2009 IEEE International Interconnect Technology Conference.

Power comparison between high-speed electrical and optical interconnects for inter-chip communication

P. Kapur, K. Saraswat, Hoyeol Cho, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

Technology and reliability constrained future copper interconnects. I. Resistance modeling

P. Kapur, K. Saraswat, J. McVittie, 2002 .

A Manufacturable, Non-Plated, Non-Ag Metallization Based 20.44% Efficient, 243cm2 Area, Back Contacted Solar Cell on 40um Thick Mono-Crystalline Silicon

P. Kapur, M. Moslehi, S. Seutter, 2013 .

Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

P. Kapur, K. Saraswat, G. Chandra, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Geometry Dependence of Poly-Si Oxidation and its Application to Self-Align, Maskless Process for Nano-scale Vertical CMOS Structures

Krishna C. Saraswat, Pawan Kapur, Pranav Kalavade, 2006 .

A very low temperature single crystal germanium growth process on insulating substrate using Ni-induced lateral crystallization for three-dimensional integrated circuits

Krishna C. Saraswat, Pawan Kapur, Hailin Peng, 2007 .

Self-nucleation free and dimension dependent metal-induced lateral crystallization of amorphous germanium for single crystalline germanium growth on insulating substrate

Krishna C. Saraswat, Pawan Kapur, Munehiro Tada, 2008 .

Low temperature boron and phosphorus activation in amorphous germanium using Ni- and Co-induced crystallization and its application for three-dimensional integrated circuits

Krishna C. Saraswat, Pawan Kapur, Munehiro Tada, 2008 .

Metal-semiconductor-metal photodetectors based on single-walled carbon nanotube film–GaAs Schottky contacts

Jason L. Johnson, A. Rinzler, P. Kapur, 2008 .

Anomalous behavior of amorphous Fe-B alloys

P. Kapur, E. Subbarao, R. Hasegawa, 1980 .

3-D ICS DSM Interconnect Performance Modeling and Analysis

Krishna C. Saraswat, Pawan Kapur, Ting-Yen Chiang, 2003 .

Technology and reliability constrained future copper interconnects. II. Performance implications

Krishna C. Saraswat, Pawan Kapur, G. Chandra, 2002 .

Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications

E. Morifuji, Y. Nishi, P. Kapur, 2007, IEEE Transactions on Electron Devices.

A Novel Spacer Process for Sub-10-nm-Thick Vertical MOS and Its Integration With Planar MOS Device

P. Kapur, P. Kalavade, Hoon Cho, 2006, IEEE Transactions on Nanotechnology.

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Kaustav Banerjee, Krishna C. Saraswat, Pawan Kapur, 2001, Proc. IEEE.

Power comparison between high-speed electrical and optical interconnects for interchip communication

P. Kapur, K.C. Saraswat, Hoyeol Cho, 2004, Journal of Lightwave Technology.

Performance Comparisons Between Cu/Low-$\kappa$ , Carbon-Nanotube, and Optics for Future On-Chip Interconnects

P. Kapur, Kyung-Hoae Koo, Hoyeol Cho, 2008, IEEE Electron Device Letters.

Power optimization of future transistors and a resulting global comparison standard

Y. Nishi, P. Kapur, R.S. Shenoy, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration

P. Kapur, M. Tada, Hyun-Yong Yu, 2008, 2008 IEEE International Electron Devices Meeting.

PERFORMANCE LIMITATIONS OF Si CMOS AND ALTERNATIVES FOR NANOELECTRONICS

C. O. Chui, P. Kapur, K. Saraswat, 2006 .

A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

P. Kapur, K.C. Saraswat, M.G. Ertosun, 2008, IEEE Electron Device Letters.

Scaling trends for the on chip power dissipation

Krishna C. Saraswat, Pawan Kapur, G. Chandra, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Highly Scalable Vertical Double Gate NOR Flash Memory

P. Kapur, K.C. Saraswat, Hoon Cho, 2007, 2007 IEEE International Electron Devices Meeting.

A Low Power, Highly Scalable, Vertical Double Gate MOSFET Using Novel Processes

Krishna C. Saraswat, Pawan Kapur, Pranav Kalavade, 2007, DRC 2007.