D. Ingerly

发表

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

P. Bai, C. Auth, S. Balakrishnan, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

R. Chau, C. Auth, M. Bost, 2007, 2007 IEEE International Electron Devices Meeting.

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, M. Bost, V. Chikarmane, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Low resistance ohmic contacts to n-GaN and n-AlGaN using NiAl

D. Ingerly, Yong Chen, Y. Chang, 2000 .

Schottky enhancement of contacts to n-(In0.52Al0.48)As using PdAl as a metallization

D. Ingerly, C. Pelto, Y. Chang, 2002 .

PdIn contacts to n-type and p-type GaP

D. Ingerly, Y. Chang, C. F. Lin, 1996 .

Impact of interfacial chemistry on adhesion and electromigration in Cu interconnects

D. Ingerly, A. Ott, C. Jan, 2004 .

Phase equilibria of the Ga–Ni–As ternary system

D. Ingerly, D. Swenson, C. Jan, 1996 .

Reply to “Comment on ‘Phase equilibria of the Ga–Ni–As ternary system’ ” [J. Appl. Phys. 82, 493 (1997)]

D. Ingerly, D. Swenson, C. Jan, 1997 .

Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

D. Pantuso, A. Balankutty, D. Ingerly, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

D. Ingerly, C. Pelto, E. Karl, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package

Sanjeev Khushu, Wilfred Gomes, Lei Jiang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

K. Mistry, J. Hicks, P. Hentges, 2012, 2012 IEEE International Interconnect Technology Conference.

Ohmic contacts to n-GaN using PtIn2

D. Ingerly, T. Kuech, N. Perkins, 1997 .

NIIN As an Ohmic Contact to P-GAN

D. Ingerly, Y. Chang, Y. Chen, 1999 .

The electrical behavior of Pt3In7 and NiIn contacts to p-GaN

D. Ingerly, Yong Chen, Y. Chang, 1999 .

PtIn 2 ohmic contacts to n-GaN

D. Ingerly, T. Kuech, N. Perkins, 1996 .