R. Nagisetty

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

P. Bai, C. Auth, S. Balakrishnan, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A 90-nm logic technology featuring strained-silicon

R. Chau, C. Auth, C. Kenyon, 2004, IEEE Transactions on Electron Devices.

100 nm gate length high performance/low power CMOS transistor structure

J. Kavalieros, C. Kenyon, R. Nagisetty, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

An advanced low power, high performance, strained channel 65nm technology

P. Bai, C. Auth, R. Heussner, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Understanding stress enhanced performance in Intel 90nm CMOS technology

R. Kotlyar, P. Matagne, C. Auth, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Organic Multi-Channel Optoelectronic Sensors for Wearable Health Monitoring

Yasser Khan, Maruf N. Ahmed, Ana C. Arias, 2019, IEEE Access.

2.5D and 3D Heterogeneous Integration: Emerging applications

R. Nagisetty, T. Karnik, F. Sheikh, 2021, IEEE Solid-State Circuits Magazine.

Multi-die Integration Using Advanced Packaging Technologies

Farhana Sheikh, Manish Deo, Ravi Mahajan, 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).