B. Woolery

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

P. Bai, C. Auth, S. Balakrishnan, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

B. Woolery, S. Pae, J. Maiz, 2008, IEEE Transactions on Device and Materials Reliability.

Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology

Mark Y. Liu, C. Parker, B. Woolery, 2010, 2010 IEEE International Reliability Physics Symposium.

Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

A. Rahman, C. Tsai, P. Bai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).