D. Gajski

发表

CEDAR: a large scale multiprocessor

Daniel Gajski, Duncan H. Lawrie, David J. Kuck, 1983, CARN.

Transaction Level Modeling in System Level Design

D. Gajski, L. Cai, 2003 .

Specification and Design of Embedded Systems

Jianwen Zhu, Daniel Gajski, Rainer Dömer, 1998, Informationstechnik Tech. Inform..

Protocol Generation for Communication Channels

Daniel Gajski, Sanjiv Narayan, D. Gajski, 1994, 31st Design Automation Conference.

Design of a GSM Vocoder using SpecC Methodology

Daniel D. Gajski, Andreas Gerstlauer, Shuqing Zhao, 1999 .

Functional verification of system level model refinements

Daniel D. Gajski, Samar Abdi, D. Gajski, 2005 .

Designing a Custom Architecture for DCT Using NISC Design Flow

Daniel Gajski, Mehrdad Reshadi, Bita Gorjiara, 2005 .

Hardware/software Partitioning And Pipelining

D. Gajski, D.D. Gajski, S. Bakshi, 1997, Proceedings of the 34th Design Automation Conference.

VLSI Design and ASPDAC Technical Program Committee

Dinesh Bhatia, Rajiv V. Joshi, Daniel D. Gajski, 2002 .

Youn-Long Steve Lin

Nikil D. Dutt, Daniel Gajski, Allen C.-H. Wu, 1992 .

IP-Centric Methodology

Daniel D. Gajski, Jianwen Zhu, Tadatoshi Ishii, 2022 .

Component selection for high-performance pipelines

Daniel Gajski, Smita Bakshi, D. Gajski, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Formal Verification of Specification Partitioning

D. Gajski, S. Abdi, 2003 .

Scheduling in RTL Design Methodology

D. Gajski, Dongwan Shin, 2000 .

Computer-Aided Synthesis of Data-Path by using a Simulated-Annealing-based approach

E. F. Girczyc, A. R. Newton, C. D. Gelatt, 1991 .

Benchmarking and the Art of Syntesis Tool Comparison

Nikil D. Dutt, Daniel Gajski, D. Gajski, 1992, Synthesis for Control Dominated Circuits.

RTOS modeling for system level design

Andreas Gerstlauer, Daniel Gajski, Haobo Yu, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Automatic Software Generation for System Level Design

D. Gajski, Haobo Yu, R. Doemer, 2003 .

SpecC Technology Open Consortium

A. Gerstlauer, D. Gajski, R. Dömer, 2001, Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573).

C01\1PUTER-AIDED PROGRA.l\1l\11NG FOR MULTIPROCESSING SYSTE1\1S

D. Gajski, Min Wu, 2015 .

An American National Standard- IEEE Standard for Binary Floating-Point Arithmetic

Robert L. Smith, James Demmel, Daniel D. Gajski, 1985 .

Grouping-Based Architecture Exploration of System-Level Design

D. Gajski, Lukai Cai, 2003 .

SpecC System-Level Design Methodology Applied to the Design of aGSM

D. Gajski, A., VocoderA, 2000 .

System Design Methodology and Tools

Daniel D. Gajski, Andreas Gerstlauer, Junyu Peng, 2003 .

Percolation based synthesis

D. Gajski, A. Nicolau, R. Potasman, 1990, 27th ACM/IEEE Design Automation Conference.

Channel Mapping in System Level Design

D. Gajski, Lukai Cai, 2003 .

SW Generation from TL to PCA Level for MPSoC

D. Gajski, S. Abdi, Ines Viskic, 2022 .

An exper-system paradigm for design

Daniel Gajski, Forrest Brewer, D. Gajski, 1988, 25 years of DAC.

Design of a JPEG Encoding System

Daniel D. Gajski, Andreas Gerstlauer, Shuqing Zhao, 1999 .

The role of learning in logic synthesis

Daniel Gajski, James R. Kipps, D. Gajski, 1989, [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence.

^SENTIAL ISSUES ^ AND POSSIBLE SOLUTIONS IN HIGH-LEVEL SYNTHESIS

D. Gajski, 2015 .

The Specc Methodology the Specc Methodology

A. Gerstlauer, D. Gajski, Jianwen Zhu, 1999 .

Specc lan-guage reference manual

Daniel D. Gajski, Andreas Gerstlauer, A. Gerstlauer, 2002 .

System-level communication modeling for network-on-chip synthesis

Andreas Gerstlauer, Daniel Gajski, Dongwan Shin, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Topic : Network and communication system Automatic Generation of Communication Architectures

A. Gerstlauer, D. Gajski, R. Dömer, 2022 .

A Programming Aid for Message-passing Systems

Daniel Gajski, Min-You Wu, D. Gajski, 1987, PPSC.

SPECC: Specification Language and Methodology

Daniel D. Gajski, D. Gajski, 2000 .

Functional Unit

Daniel D. Gajski, D. Gajski, Poonam Agrawal, 1996 .

Modeling flow for automated system design and exploration

Daniel D. Gajski, Andreas Gerstlauer, A. Gerstlauer, 2004 .

OpenJ: an extensible system level design language

Jianwen Zhu, Daniel Gajski, D. Gajski, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Panel: Opportunities and pitfalls in HDL-based system design

Rajesh K. Gupta, Daniel Gajski, Yatin Trivedi, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Timing models for high-level synthesis

Viraphol Chaiyakul, Daniel Gajski, Allen C.-H. Wu, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Hypertool: A Programming Aid for Message-Passing Systems

Daniel Gajski, Min-You Wu, D. Gajski, 1990, IEEE Trans. Parallel Distributed Syst..

Essential issues for IP reuse

V. Chaiyakul, D.D. Gajski, A.C.-H. Wu, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Embedded tutorial: essential issues for IP reuse

Daniel D. Gajski, Viraphol Chaiyakul, Allen C.-H. Wu, 2000, ASP-DAC '00.

Implementing flexible hybrid instruction in an electrical engineering course: The best of three worlds?

Daniel Gajski, Mark Warschauer, George Farkas, 2015, Comput. Educ..

A transformation-based method for loop folding

Daniel Gajski, Youn-Long Lin, Allen C.-H. Wu, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Essential Issues and Possible Solutions in High-Level Synthesis

Daniel D. Gajski, D. Gajski, 1991 .

High ― Level Synthesis: Introduction to Chip and System Design

Daniel D. Gajski, Nikil Dutt, Allen C.-H. Wu, 1992 .

An Introduction to High-Level Synthesis

Daniel Gajski, Loganath Ramachandran, D. Gajski, 2009, IEEE Design & Test of Computers.

Structural operational semantics for supporting multi-cycle operations in RTL HDLs

Daniel Gajski, Shuqing Zhao, D. Gajski, 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

Reuse and protection of intellectual property in the SpecC system

Daniel Gajski, Rainer Dömer, D. Gajski, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

RTOS modeling for system level design

Andreas Gerstlauer, Daniel Gajski, Haobo Yu, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A new algorithm for transistor sizing in CMOS circuits

Daniel Gajski, Allen C.-H. Wu, Nels Vander Zanden, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

A parallel pipelined relational query processor: An architectural overview

Won Kim, Daniel Gajski, Shinya Fushimi, 1989, ISCA '84.

Introduction of Design-Oriented Profiler of SpecC Language

Daniel D. Gajski, Lukai Cai, D. Gajski, 2002 .

SpecC System-Level Design Methodology Applied to the Design of a GSM Vocoder

Daniel D. Gajski, Andreas Gerstlauer, Shi-Ming Zhao, 2000 .

SpecCharts: a VHDL front-end for embedded systems

Frank Vahid, Daniel Gajski, Sanjiv Narayan, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A system-design methodology: executable-specification refinement

Frank Vahid, Daniel Gajski, Sanjiv Narayan, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Specification partitioning for system design

Frank Vahid, Daniel Gajski, D. Gajski, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

An effective methodology for functional pipelining

Daniel D. Gajski, Youn-Long Lin, Allen C.-H. Wu, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Embedded System Design: Modeling, Synthesis and Verification

Daniel D. Gajski, Andreas Gerstlauer, Samar Abdi, 2013 .

Transaction level modeling: an overview

Daniel Gajski, Lukai Cai, D. Gajski, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

System specification with the SpecCharts language

Frank Vahid, Daniel Gajski, Sanjiv Narayan, 1992, IEEE Design & Test of Computers.

The role of learning in logic synthesis

D. Gajski, J. Kipps, 1989, [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence.

Computer-aided programming for message-passing systems: problems and solutions

M.-Y. Wu, D. D. Gajski, D. Gajski, 1989, Proc. IEEE.

A programming aid for hypercube architectures

Daniel Gajski, Min-You Wu, D. Gajski, 1988, The Journal of Supercomputing.

An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors

Andreas Gerstlauer, Daniel Gajski, Dongwan Shin, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A novel memory size model for variable-mapping in system level design

D. Gajski, Haobo Yu, Lukai Cai, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Modeling a new RTL semantics in C++

Daniel Gajski, Shuqing Zhao, D. Gajski, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

RTL semantics and methodology

Daniel Gajski, Brian Bailey, D. Gajski, 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

Usage-based characterization of complex functional blocks for reuse in behavioral synthesis

Nong Fan, V. Chaiyakul, D.D. Gajski, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Soft scheduling in high level synthesis

Jianwen Zhu, D. Gajski, Jianwen Zhu, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

A unified formal model of ISA and FSMD

J. Zhu, D. Gajski, Jianwen Zhu, 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

RT level power analysis

D.D. Gajski, J.-W. Zhu, P. Agrawal, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Methodology is the future

D. D. Gajski, D. Gajski, 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

Clock optimization for high-performance pipelined design

Daniel Gajski, Smita Bakshi, Hsiao-Ping Juan, 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

Clock-driven performance optimization in interactive behavioral synthesis

Viraphol Chaiyakul, Daniel Gajski, Hsiao-Ping Juan, 1996, Proceedings of International Conference on Computer Aided Design.

Architectural exploration for datapaths with memory hierarchy

Daniel Gajski, Nancy D. Holmes, N. D. Holmes, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Condition Graphs For High-quality Behavioral Synthesis

Daniel D. Gajski, Viraphol Chaiyakul, Hsiao-Ping Juan, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Introduction to high-level synthesis

Daniel Gajski, Michael Meredith, Philippe Coussy, 1994, IEEE Design & Test of Computers.

An algorithm for array variable clustering

Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Top-down modeling of RISC processors in VHDL

Daniel Gajski, Smita Bakshi, Hsiao-Ping Juan, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

High-Level Transformations for Minimizing Syntactic Variances

Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran, 1993, 30th ACM/IEEE Design Automation Conference.

Accurate layout area and delay modeling for system level design

V. Chaiyakul, C. Ramachandran, F. J. Kurdahi, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

An efficient multi-view design model for real-time interactive synthesis

Daniel D. Gajski, Tedd Hadley, Allen C.-H. Wu, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

A retargetable, ultra-fast instruction set simulator

Daniel D. Gajski, Jianwen Zhu, D. Gajski, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

A case study to develop a graduate-level degree program in embedded & cyber-physical systems

Ahmed M. Eltawil, Fadi J. Kurdahi, Daniel Gajski, 2017, SIGBED.

An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines

Daniel Gajski, D. Gajski, 1981, IEEE Transactions on Computers.

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design

Frank Vahid, Daniel Gajski, Jie Gong, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Sysiem Specification with he

Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, 1992 .

Parallelization Optimization of System-Level Specification

Daniel D. Gajski, Lukai Cai, D. Gajski, 2002 .

Specification Tuning of System-Level Design

Daniel D. Gajski, Lukai Cai, D. Gajski, 2002 .

Essential Issues in Multiprocessor Systems

Daniel Gajski, Jih-Kwon Peir, D. Gajski, 1985, Computer.

Flow Graph Representation

Daniel Gajski, Alex Orailoglu, D. Gajski, 1986, 23rd ACM/IEEE Design Automation Conference.

Verification of System Level Model Transformations

Daniel Gajski, Samar Abdi, D. Gajski, 2006, International Journal of Parallel Programming.

A formalism for functionality preserving system level transformations

D. Gajski, S. Abdi, D. Gajski, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Automatic generation of equivalent architecture model from functional specification

Daniel Gajski, Samar Abdi, D. Gajski, 2004, Proceedings. 41st Design Automation Conference, 2004..

On deriving equivalent architecture model from system specification

Daniel Gajski, Samar Abdi, D. Gajski, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

System design methodologies: aiming at the 100 h design cycle

Frank Vahid, Daniel Gajski, Sanjiv Narayan, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Specification and Design of Embedded Hardware-Software Systems

Frank Vahid, Daniel Gajski, D. Gajski, 1995, IEEE Des. Test Comput..

100-hour design cycle: a test case

Frank Vahid, Daniel Gajski, Sanjiv Narayan, 1994, EURO-DAC '94.

System specification and synthesis with the SpecCharts language

Frank Vahid, Daniel Gajski, Sanjiv Narayan, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Obtaining functionally equivalent simulations using VHDL and a time-shift transformation

Frank Vahid, Daniel Gajski, D. Gajski, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Comparison of five multiprocessor systems

Daniel Gajski, Jih-Kwon Peir, D. Gajski, 1985, Parallel Comput..

Automatic architecture refinement techniques for customizing processing elements

Daniel Gajski, Bita Gorjiara, D. Gajski, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Design synthesis and silicon compilation

Nikil D. Dutt, Daniel Gajski, D. Gajski, 1990, IEEE Design & Test of Computers.

Early performance-cost estimation of application-specific data path pipelining

Daniel Gajski, Jelena Trajkovic, D. Gajski, 2010, 2010 IEEE 8th Symposium on Application Specific Processors (SASP).

Bringing in-class online - A hybrid solution

Daniel D. Gajski, Quoc-Viet Dang, D. Gajski, 2014, Fourth Interdisciplinary Engineering Design Education Conference.

Chippe: a system for constraint driven behavioral synthesis

Daniel Gajski, Forrest Brewer, D. Gajski, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automating technology adaptation in design synthesis

Daniel D. Gajski, James Randall Kipps, D. Gajski, 1989 .

Hypertool: A Programming Aid for Multicomputers

Daniel Gajski, Min-You Wu, D. Gajski, 1989, International Conference on Parallel Processing.

High ― Level Synthesis: Introduction to Chip and System Design

D. Gajski, N. Dutt, A. Wu, 1992 .

Youn-Long Steve Lin

Minh N. Do, Deming Chen, Yun Liang, 1992 .

A memory selection algorithm for high-performance pipelines

Daniel Gajski, Smita Bakshi, D. Gajski, 1995, Proceedings of EURO-DAC. European Design Automation Conference.

Component synthesis from functional descriptions

Elke A. Rundensteiner, Daniel Gajski, Lubomir F. Bic, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cycle-approximate Retargetable Performance Estimation at the Transaction Level

Daniel Gajski, Samar Abdi, Yonghyun Hwang, 2008, 2008 Design, Automation and Test in Europe.

Retargetable profiling for rapid, early system-level design space exploration

Andreas Gerstlauer, Daniel Gajski, Lukai Cai, 2004, Proceedings. 41st Design Automation Conference, 2004..

Generic netlist representation for system and PE level design exploration

Daniel Gajski, Mehrdad Reshadi, Bita Gorjiara, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs

Daniel Gajski, Mehrdad Reshadi, Bita Gorjiara, 2006, 2006 International Conference on Computer Design.