B. Cao

发表

Performance analysis of different special moduli sets for RNS-based inner product step processor

Jeremy Yung Shern Low, Chip-Hong Chang, B. Cao, 2010, The 2010 International Conference on Green Circuits and Systems.

An efficient reverse converter for the 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup 2n/ + 1} based on the new Chinese remainder theorem

Chip-Hong Chang, B. Cao, T. Srikanthan, 2003 .

An Efficient Reverse Converter for the 4-Moduli Set 2 n 1 , 2 n , 2 n + 1 , 22 n + 1 Based on the New Chinese Remainder Theorem

Chip-Hong Chang, B. Cao, T. Srikanthan, 2001 .

A Residue-to-Binary Converter for a New Five-Moduli Set

Chip-Hong Chang, Bin Cao, Thambipillai Srikanthan, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Efficient reverse converters for four-moduli sets { 2n−1, 2n, 2n+1, 2n+1−1} and {2n−1, 2n, 2n+1, 2n−1−1}

Chip-Hong Chang, B. Cao, T. Srikanthan, 2005 .

Efficient reverse converters for four-moduli sets {2^n-1, 2^n, 2^n+1, 2^n^+^1-1} and {2^n-1, 2^n, 2^n+1, 2^n^-^1-1}

B. Cao, T. Srikanthan, 2005 .

Adder based residue to binary converters for a new balanced 4-moduli set

B. Cao, T. Srikanthan, C.-H. Chang, 2003, 3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the.

Design of a high speed reverse converter for a new 4-moduli set residue number system

Chip-Hong Chang, T. Srikanthan, Bin Cao, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

New efficient residue-to-binary converters for 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup n+1/ - 1}

Chip-Hong Chang, Bin Cao, Thambipillai Srikanthan, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An Efficient Reverse Converter for the 4-Moduli Set , , , Based on the New

Chip-Hong Chang, Thambipillai Srikanthan, Bin Cao, 2003 .

Directional view method for a time-sequential autostereoscopic display with full resolution.

Song Guo, Zhenfeng Zhuang, Phil Surman, 2016, Applied optics.

Area-Time Efficient FAST Corner Detector Using Data-Path Transposition

Bin Cao, Meiqing Wu, Siew-Kei Lam, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector

Bin Cao, Meiqing Wu, Siew-Kei Lam, 2017, Journal of Real-Time Image Processing.