S. Piestrak

发表

A high-speed realization of a residue to binary number system converter

S. Piestrak, 1995 .

The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes

Stanislaw J. Piestrak, S. Piestrak, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Efficient Hamming weight comparators of binary vectors

S. Piestrak, 2007 .

Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture : A Case Study

Syed M. A. H. Jafri, S. Piestrak, O. Sentieys, 2010 .

RNS Number Comparator Based on a Modified Diagonal Function

S. Piestrak, A. Tchernykh, M. Babenko, 2020 .

Design of cost-efficient multipliers modulo 2a−1

Stanislaw J. Piestrak, S. Piestrak, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor

Sébastien Pillement, Stanislaw J. Piestrak, Hung-Manh Pham, 2013, IEEE Transactions on Computers.

Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes

Stanislaw J. Piestrak, Piotr Patronik, S. Piestrak, 2014, 2014 17th Euromicro Conference on Digital System Design.

Error recovery technique for coarse-grained reconfigurable architectures

Olivier Sentieys, Sébastien Pillement, Stanislaw J. Piestrak, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

The Study of Monotonic Core Functions and Their Use to Build RNS Number Comparators

Stanislaw J. Piestrak, Nikolay I. Chervyakov, Mikhail Babenko, 2021 .

Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem

Stanislaw J. Piestrak, S. Piestrak, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Design of residue generators and multioperand modular adders using carry-save adders

Stanislaw J. Piestrak, S. Piestrak, 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

Implementation and evaluation of configuration scrubbing on CGRAs: A case study

Hannu Tenhunen, Juha Plosila, Stanislaw J. Piestrak, 2013, 2013 International Symposium on System on Chip (SoC).

On the design of self-testing checkers for modified Berger codes

Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos, 2001, Proceedings Seventh International On-Line Testing Workshop.

Design of Fast Self-Testing Checkers for a Class of Berger Codes

Stanislaw J. Piestrak, S. Piestrak, 1987, IEEE Transactions on Computers.

Design of Fault-Secure Multipliers-Accumulators and {FIR} Filters Protected Using Residue Codes

Stanislaw J. Piestrak, Piotr Patronik, S. Piestrak, 2014, Euromicro Symposium on Digital Systems Design.