Y. Chih

发表

Ultra high density 3D via RRAM in pure 28nm CMOS process

M. Tsai, M. Hsieh, Yu-Cheng Liao, 2013, 2013 IEEE International Electron Devices Meeting.

Embedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications

Meng-Fan Chang, Yu-Der Chih, Ya-Chin King, 2017, 2017 Symposium on VLSI Circuits.

A 40nm 2Mb ReRAM Macro with 85% Reduction in FORMING Time and 99% Reduction in Page-Write Time Using Auto-FORMING and Auto-Write Schemes

Y. Chih, Meng-Fan Chang, T. Chang, 2019, 2019 Symposium on VLSI Technology.

1Kbit FinFET Dielectric (FIND) RRAM in pure 16nm FinFET CMOS logic process

Y. Chih, Y. King, C. Lin, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Y. Chih, Y. King, C. Lin, 2017 .

A high density Twin-Gate OTP cell in pure 28nm CMOS process

Tzong-Sheng Chang, Y. Chih, Y. King, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays

M. Tsai, M. Hsieh, Yu-Cheng Liao, 2014, IEEE Journal of the Electron Devices Society.

Embedded Near-Infrared Sensor With Tunable Sensitivity for Nanoscale CMOS Technologies

Y. Chih, Y. King, C. Lin, 2019, IEEE Sensors Journal.

Gate contact resistive random access memory in nano scaled FinFET logic technologies

Y. Chih, Y. King, C. Lin, 2017 .

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

Yen-Cheng Chiu, Yu-Der Chih, Cheng-Xin Xue, 2021, IEEE Journal of Solid-State Circuits.

Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film‐Based Gas Sensors by Floating‐Gate Coupling Effect

Y. Chih, Y. King, C. Lin, 2021, Advanced Functional Materials.

Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology

Y. Chih, Y. King, C. Lin, 2022, Nanoscale Research Letters.

Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches

Y. Chih, Y. King, Jonathan Chang, 2020, IEEE Transactions on Electron Devices.

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator

David Blaauw, Dennis Sylvester, Hun-Seok Kim, 2021, IEEE Journal of Solid-State Circuits.

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination

David Blaauw, Dennis Sylvester, Yu-Der Chih, 2019, IEEE Journal of Solid-State Circuits.

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding

Y. Chih, Meng-Fan Chang, A. Raychowdhury, 2022, IEEE Journal of Solid-State Circuits.

Differential Contact RRAM Pair for Advanced CMOS Logic NVM applications

Ya-Chin King, W.-T. Hsieh, C.-J. Lin, 2017 .

1-kb FinFET Dielectric Resistive Random Access Memory Array in $1\times $ nm CMOS Logic Technology for Embedded Nonvolatile Memory Applications

Y. Chih, Y. King, C. Lin, 2016, IEEE Transactions on Electron Devices.

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Yen-Cheng Chiu, Wei-Chen Wei, Ren-Shuo Liu, 2020, Nature Electronics.

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices

Y. Chih, C. Lo, Meng-Fan Chang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Hidehiro Fujiwara, Tan-Li Chou, Yu-Der Chih, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Y. Chih, C. Lo, Meng-Fan Chang, 2020, Nature Electronics.

Multifunctional Ion-Sensitive Floating Gate Fin Field-Effect Transistor with Three-Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology.

Y. Chih, Y. King, C. Lin, 2021, Small.

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Meng-Fan Chang, Shu-Meng Yang, Che-Wei Wu, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range

Y. Chih, Meng-Fan Chang, A. Raychowdhury, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

Y. Chih, K. Akarvardar, Yih Wang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process

Y. Chih, Chieh-Pu Lo, H. Chuang, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme

Yu-Der Chih, Tsung-Yung Jonathan Chang, Shau-Yu Chou, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process

Ming-Jinn Tsai, Ya-Chin King, Shyh-Shyuan Sheu, 2012, 2012 International Electron Devices Meeting.

Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology

Y. Chih, Y. King, C. Lin, 2021, Nanoscale Research Letters.

28-nm 2T High-$K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Frederick T. Chen, Ming-Jinn Tsai, Yue-Der Chih, 2013, IEEE Electron Device Letters.

A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices

Y. Chih, C. Lo, Meng-Fan Chang, 2021, Nature Electronics.

A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2011, IEEE Transactions on Electron Devices.

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM

David Blaauw, Dennis Sylvester, Yu-Der Chih, 2018, 2018 IEEE Symposium on VLSI Circuits.

Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Meng-Fan Chang, Yen-Chen Liu, Yu-Der Chih, 2015, IEEE Journal of Solid-State Circuits.

Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology

Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, 2019, Sensors.

CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

Boris Murmann, Yu-Der Chih, Subhasish Mitra, 2021, 2021 Symposium on VLSI Circuits.

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Arijit Raychowdhury, Yu-Der Chih, Win-San Khwa, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection

Arijit Raychowdhury, Yu-Der Chih, Win-San Khwa, 2022, IEEE Journal of Solid-State Circuits.

An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance

Chung-Cheng Chou, Pei-Ling Tseng, Yu-Der Chih, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

High Resolution Ion Detector (HRID) by 16nm FinFET CMOS Technology

Peng-Chun Liou, Yu-Lun Chueh, Jonathan Chang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate

Yue-Der Chih, Ya-Chin King, Kai-Chun Lin, 2009, IEEE Electron Device Letters.

Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications

Y. Chih, T. Chang, Chung-Cheng Chou, 2021, International Electron Devices Meeting.

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations

Y. Chih, C. Lo, Chieh-Pu Lo, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity

Y. Chih, C. Kuo, Yih Wang, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices

Y. Chih, C. Lo, Meng-Fan Chang, 2023, IEEE Journal of Solid-State Circuits.

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

Y. Chih, T. Chang, H. Fujiwara, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory

Y. Chih, Y. King, C. Lin, 2023, IEEE Transactions on Electron Devices.

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range

Chung-Cheng Chou, Zheng-Jun Lin, Chien-An Lai, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking

Y. Chih, Meng-Fan Chang, A. Raychowdhury, 2023, IEEE International Solid-State Circuits Conference.

A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems

Y. Chih, Meng-Fan Chang, A. Raychowdhury, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation

Arijit Raychowdhury, Yu-Der Chih, Win-San Khwa, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference

Yu-Lin Chen, Harry Chuang, Yu-Der Chih, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes

David Blaauw, Dennis Sylvester, Yejoong Kim, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Meng-Fan Chang, Hiroyuki Yamauchi, Che-Wei Wu, 2013, IEEE Journal of Solid-State Circuits.

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Meng-Fan Chang, Sreedhar Natarajan, Yu-Der Chih, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices

Y. Chih, C. Lo, Chieh-Pu Lo, 2023, Nature Electronics.

Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage

Yue-Der Chih, Ya-Chin King, Yi-Hong Chang, 2019, IEEE Journal of Solid-State Circuits.

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM

David Blaauw, Dennis Sylvester, Li Xu, 2020, 2020 IEEE Symposium on VLSI Circuits.