B. Rajendran

发表

Phase change memory technology

K. Gopalakrishnan, M. Breitwisch, G. Burr, 2010, 1001.1164.

Analytical model for RESET operation of Phase Change Memory

G.W. Burr, C. Lam, B. Rajendran, 2008, 2008 IEEE International Electron Devices Meeting.

On the dynamic resistance and reliability of phase change memory

M. Breitwisch, G. Burr, Y. Shih, 2008, 2008 Symposium on VLSI Technology.

Novel Lithography-Independent Pore Phase Change Memory

M. Breitwisch, G. Burr, Yi-Chou Chen, 2007, 2007 IEEE Symposium on VLSI Technology.

Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory

C. Lam, B. Rajendran, T. Happ, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Nanoscale electronic synapses using phase change devices

Geoffrey W. Burr, Dharmendra S. Modha, Bryan L. Jackson, 2013, JETC.

A phase-change memory model for neuromorphic computing

E. Eleftheriou, B. Rajendran, A. Sebastian, 2018, Journal of Applied Physics.

Arbitrary Spike Time Dependent Plasticity (STDP) in Memristor by Analog Waveform Engineering

B. Rajendran, N. Panwar, U. Ganguly, 2017, IEEE Electron Device Letters.

Neuromorphic Computing Based on Emerging Memory Technologies

B. Rajendran, F. Alibart, 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Supervised learning in spiking neural networks with MLC PCM synapses

B. Rajendran, S. R. Nandakumar, A. Sebastian, 2017, 2017 75th Annual Device Research Conference (DRC).

System-level integration in neuromorphic co-processors

B. Rajendran, D. Querlioz, 2020 .

Novel Biomimetic Si Devices for Neuromorphic Computing Architecture

B. Rajendran, U. Ganguly, 2017 .

Modeling and Simulation of 1/f Noise During Threshold Switching for Phase Change Memory

B. Rajendran, M. Baghini, R. Parekh, 2018 .

Bio-mimetic Synaptic Plasticity and Learning in a sub-500mV Cu/SiO2/W Memristor

B. Rajendran, S. Nandakumar, 2020, ArXiv.

Phase Change Memory: From Devices to Systems

Sudhanva Gurumurthi, Moinuddin K. Qureshi, Bipin Rajendran, 2011, Phase Change Memory.

Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

Y.C. Chen, M. Breitwisch, R. Bergmann, 2007, 2007 IEEE International Electron Devices Meeting.

Efficient scrub mechanisms for error-prone emerging memories

Vijayalakshmi Srinivasan, Rajeev Balasubramonian, Kshitij Sudan, 2012, IEEE International Symposium on High-Performance Comp Architecture.

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Jae-sun Seo, Shihui Yin, Bipin Rajendran, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Shihui Yin, Jae-Sun Seo, Bipin Rajendran, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Building Brain-Inspired Computing Systems: Examining the Role of Nanoscale Devices

Bipin Rajendran, Shruti R. Kulkarni, Anakha V. Babu, 2018, IEEE Nanotechnology Magazine.

Neuromorphic computing with multi-memristive synapses

Yusuf Leblebici, Thomas P. Parnell, Evangelos Eleftheriou, 2017, Nature Communications.

Accurate deep neural network inference using computational phase-change memory

Evangelos Eleftheriou, S. R. Nandakumar, Irem Boybat, 2019, Nature Communications.

Mixed-precision architecture based on computational memory for training deep neural networks

Evangelos Eleftheriou, S. R. Nandakumar, Irem Boybat, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Spiking Generative Adversarial Networks With a Neural Network Discriminator: Local Training, Bayesian Models, and Continual Meta-Learning pdf

Osvaldo Simeone, Bipin Rajendran, Bleema Rosenfeld, 2021, IEEE Transactions on Computers.

Spiking neural networks for handwritten digit recognition - Supervised learning and network optimization

Bipin Rajendran, Shruti R. Kulkarni, B. Rajendran, 2018, Neural Networks.

Learning and real-time classification of hand-written digits with spiking neural networks

Bipin Rajendran, Shruti R. Kulkarni, John M. Alexiades, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Adversarial Training for Probabilistic Spiking Neural Networks

Alireza Bagheri, Osvaldo Simeone, Bipin Rajendran, 2018, 2018 IEEE 19th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC).

Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems

Yong Liu, Leland Chang, K. Gopalakrishnan, 2013, IEEE Transactions on Electron Devices.

Experimental Demonstration of Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses

Evangelos Eleftheriou, Bipin Rajendran, S. R. Nandakumar, 2019, Scientific Reports.

Novel synaptic memory device for neuromorphic computing

Bipin Rajendran, Rashmi Jha, Ammaarah El-Amin, 2014, Scientific Reports.

Low Thermal Budget Processing for Sequential 3-D IC Fabrication

B. Rajendran, R. Shenoy, B. Rajendran, 2007, IEEE Transactions on Electron Devices.

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Osvaldo Simeone, Bipin Rajendran, Abu Sebastian, 2020, Adv. Intell. Syst..

Mixed-Precision Deep Learning Based on Computational Memory

E. Eleftheriou, B. Rajendran, A. Sebastian, 2020, Frontiers in Neuroscience.

Acceleration of Convolutional Networks Using Nanoscale Memristive Devices

Bipin Rajendran, Shruti R. Kulkarni, Anakha V. Babu, 2018, EANN.

Phase Change Memory

H.-S. Philip Wong, Simone Raoux, Mehdi Asheghi, 2010, Proceedings of the IEEE.

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

B. Rajendran, R. Dasaka, M. Breitwisch, 2009, IEEE Electron Device Letters.

Fast On-Device Adaptation for Spiking Neural Networks Via Online-Within-Online Meta-Learning

B. Rajendran, O. Simeone, Bleema Rosenfeld, 2021, 2021 IEEE Data Science and Learning Workshop (DSLW).

Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC

Albert K. Henning, Bipin Rajendran, Zvi Or-Bach, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Learning First-to-Spike Policies for Neuromorphic Control Using Policy Gradients

Osvaldo Simeone, Bipin Rajendran, Bleema Rosenfeld, 2018, 2019 IEEE 20th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC).

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

Yong Liu, Bernard Brezzo, Daniel J. Friedman, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Reducing read latency of phase change memory via early read and Turbo Read

Moinuddin K. Qureshi, Chia-Chen Chou, Bipin Rajendran, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Phase-Change Memory Models for Deep Learning Training and Inference

Irem Boybat, Manuel Le Gallo, Abu Sebastian, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Erratum to: Novel Biomimetic Si Devices for Neuromorphic Computing Architecture

Bipin Rajendran, Udayan Ganguly, B. Rajendran, 2017 .

Endurance Improvement of Ge2Sb2Te5-Based Phase Change Memory

B. Rajendran, H. L. Lung, M. Breitwisch, 2009, 2009 IEEE International Memory Workshop.

A 250 mV Cu/SiO2/W Memristor with Half-Integer Quantum Conductance States.

Catherine Dubourdieu, Bipin Rajendran, B. Rajendran, 2016, Nano letters.

Coding for sensing in Content Addressable Memories

Bipin Rajendran, Luis Alfonso Lastras-Montaño, Michele Franceschini, 2010, 2010 IEEE International Symposium on Information Theory.

Analytics for A Controlled Experiment to Determine Optimal Thermal Insulation for Building Envelopes

Monika Jain, Bipin Rajendran, Gagan Deep Singh, 2015, Building Simulation Conference Proceedings.

Kinetic Monte Carlo Simulation of Interface-Controlled Hafnia-Based Resistive Memory

B. Rajendran, M. Anantram, Xu Xu, 2020, IEEE Transactions on Electron Devices.

Computational memory-based inference and training of deep neural networks

B. Rajendran, S. R. Nandakumar, A. Petropoulos, 2019, 2019 Symposium on VLSI Technology.

Embedded tutorial - Can silicon machines match the efficiency of the human brain?

Bipin Rajendran, B. Rajendran, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Low-Power Neuromorphic Hardware for Signal Processing Applications: A review of architectural and system-level design approaches

Narayan Srinivasa, Evangelos Eleftheriou, Abu Sebastian, 2019, IEEE Signal Processing Magazine.

Spiking neural networks — Algorithms, hardware implementations and applications

Bipin Rajendran, Shruti R. Kulkarni, Anakha V. Babu, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity

B. Rajendran, O. Simeone, B. Al-Hashimi, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

Thermal considerations for monolithic integration of three-dimensional integrated circuits

B. Rajendran, A. Henning, B. Cronquist, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Impact of conductance drift on multi-PCM synaptic architectures

Yusuf Leblebici, Evangelos Eleftheriou, S. R. Nandakumar, 2018, 2018 Non-Volatile Memory Technology Symposium (NVMTS).

Lamellar crystallization of silicon for 3-dimensional integration

Piero Pianetta, Roger Fabian W. Pease, Bipin Rajendran, 2007 .

Energy-Efficient On-Board Radio Resource Management for Satellite Communications via Neuromorphic Computing

B. Rajendran, S. Chatzinotas, O. Simeone, 2023, arXiv.org.

Stochastic learning in deep neural networks based on nanoscale PCMO device characteristics

Bipin Rajendran, Udayan Ganguly, Anakha V. Babu, 2018, Neurocomputing.

Memristive devices as computational memory

Damien Querlioz, Abu Sebastian, Bipin Rajendran, 2020 .

Demonstration of CAM and TCAM Using Phase Change Devices

Chung Lam, Luis A. Lastras, Jing Li, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

A neural circuit for navigation inspired by C. elegans Chemotaxis pdf

Shibani Santurkar, Bipin Rajendran, B. Rajendran, 2014, arXiv.org.

Characterization and Modeling

Bipin Rajendran, B. Rajendran, 2017 .

Training Probabilistic Spiking Neural Networks with First- To-Spike Decoding

Alireza Bagheri, Osvaldo Simeone, Bipin Rajendran, 2017, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Mixed-Precision Deep Learning Based on Computational Memory

Theodore Antonakopoulos, Evangelos Eleftheriou, Bipin Rajendran, 2020, Frontiers in Neuroscience.

Building Next-Generation AI systems: Co-Optimization of Algorithms, Architectures, and Nanoscale Memristive Devices

Evangelos Eleftheriou, Abu Sebastian, Bipin Rajendran, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

Mixed-precision training of deep neural networks using computational memory pdf

Evangelos Eleftheriou, S. R. Nandakumar, Irem Boybat, 2017, ArXiv.

A 250 mV Cu/SiO2/W Memristor with Half-Integer Quantum Conductance States.

B. Rajendran, M. Minvielle, C. Dubourdieu, 2016, Nano letters.

Increasing reconfigurability with memristive interconnects

Simha Sethumadhavan, Steven M. Nowick, Bipin Rajendran, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

SpinAPS: A High-Performance Spintronic Accelerator for Probabilistic Spiking Neural Networks pdf

Osvaldo Simeone, Bipin Rajendran, Anakha V Babu, 2020, ArXiv.

Mechanisms of retention loss in Ge2Sb2Te5-based Phase-Change Memory

B. Rajendran, R. Dasaka, Y. Zhu, 2008, 2008 IEEE International Electron Devices Meeting.

Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni, B. Rajendran, Jae-sun Seo, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).