C. Hu

Kaustav Banerjee, A. Amerasekera, Chenming Hu, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications

C. Hu, H. Iwai, S. Salahuddin, 2016 .

Body self bias in fully depleted and non-fully depleted SOI devices

Mansun Chan, Ping Keung Ko, Chenming Hu, 1994, Proceedings. IEEE International SOI Conference.

Ultrathin body InAs tunneling field-effect transistors on Si substrates

Elena Plis, Sanjay Krishna, Chenming Hu, 2011 .

Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model

Chenming Hu, Yogesh Singh Chauhan, Sourabh Khandelwal, 2014, IEEE Electron Device Letters.

Methods for Extracting Flat Band Voltage in the InGaAs High Mobility Materials

C. Hu, Yueh-Chin Lin, Q. Luc, 2016, IEEE Electron Device Letters.

Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition

C. Hu, Y. Chauhan, A. Agarwal, 2018, IEEE Transactions on Electron Devices.

Sub-50nm FinFET : PMOS

Vivek Subramanian, Jeffrey Bokor, Chenming Hu, 1999 .

Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability

Chenming Hu, K. F. Schuegraf, C. Hu, 1994 .

Effects of temperature and defects on breakdown lifetime of thin SiO/sub 2/ at very low voltages

Chenming Hu, K. F. Schuegraf, C. Hu, 1994 .

Effects of temperature and defects on breakdown lifetime of thin SiO/sub 2/ at very low voltages

Chenming Hu, K. F. Schuegraf, C. Hu, 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

Interface characterization of fully-depleted SOI MOSFET by a subthreshold I-V method

Bin Yu, C. Hu, P. Ko, 1994, Proceedings. IEEE International SOI Conference.

Dc electrical oxide thickness model for quantization of the inversion layer in MOSFETs

Ya-Chin King, Chenming Hu, Y. King, 1998 .

FinFET-a quasi-planar double-gate MOSFET

J. Bokor, Chenming Hu, Xuejue Huang, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Small signal electron charge centroid model for quantization of inversion layer in a metal-on-insulator field-effect transistor

Y. King, C. Hu, S. Kamohara, 1998 .

A compact model to predict quantized sub-band energy levels and inversion layer centroids of MOSFETs with a parabolic potential well approximation

C. Hu, Yu Wang, M. Chan, 2005 .

Advanced Compact Models for MOSFETs

C. Hu, G. Gildenblat, C. Enz, 2005 .

Temperature acceleration of time-dependent dielectric breakdown

Chenming Hu, Jeong-Soo Lee, R. Moazzami, 1989 .

Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions

Elyse Rosenbaum, Chenming Hu, C. Hu, 1993 .

Accelerated testing of SiO/sub 2/ reliability

Elyse Rosenbaum, Chenming Hu, C. Hu, 1996 .

Simulating process-induced gate oxide damage in circuits

Chenming Hu, Hyungcheol Shin, C. Hu, 1997 .

Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers

Chenming Hu, P. K. Ko, Jone-Fang Chen, 1992 .

High-gain monolithic 3D CMOS inverter using layered semiconductors

C. Hu, A. Javey, A. Sachid, 2017 .

Field-E ff ect Transistors Built from All Two-DimensionalMaterialComponents

C. Hu, A. Javey, A. Sachid, 2014 .

Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's

Ping-Keung Ko, Jeong Yeol Choi, Chenming Hu, 1986 .

Impact of polysilicon depletion in thin oxide MOS technology

Chenming Hu, K. F. Schuegraf, C. Hu, 1993, 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.

Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

C. Hu, A. Sachid, Hsiang-Yun Lin, 2017, IEEE Transactions on Electron Devices.

A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

C. Hu, Chun-Chi Chen, Jan-Tsai Liu, 2011, IEEE Transactions on Electron Devices.

Linearly graded doping drift region: A novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances

C. Hu, M. Chan, Ru Huang, 2002 .

Noise overshoot at drain current kink in SOI MOSFET

Ping-Keung Ko, Chenming Hu, C. G. Sodini, 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.

A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect

Chetan Kumar Dabhi, C. Hu, Y. Chauhan, 2018, 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model

C. Hu, A. Sachid, S. Salahuddin, 2017, IEEE Transactions on Electron Devices.

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Chenming Hu, Pragya Kushwaha, Sayeef Salahuddin, 2018, IEEE Transactions on Electron Devices.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

Chenming Hu, Yi-Ju Chen, Lain-Jong Li, 2014, 2014 IEEE International Electron Devices Meeting.

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

C. Hu, A. Sachid, S. Salahuddin, 2018, IEEE Transactions on Electron Devices.

NCFET Design Considering Maximum Interface Electric Field

Chenming Hu, Pragya Kushwaha, Sayeef Salahuddin, 2018, IEEE Electron Device Letters.

Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs

Y. Yeo, C. Hu, T. King, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

BSIM5 MOSFET Model

Mansun Chan, Jin He, Chenming Hu, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET

Chetan Kumar Dabhi, C. Hu, Y. Chauhan, 2018, IEEE Microwave and Wireless Components Letters.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

C. Hu, Y. Chauhan, A. Dasgupta, 2017, IEEE Transactions on Microwave Theory and Techniques.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

C. Hu, A. Sachid, S. Salahuddin, 2017, IEEE Transactions on Electron Devices.

Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model

C. Hu, Y. Chauhan, P. Ye, 2016, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport

Chenming Hu, Pragya Kushwaha, Sayeef Salahuddin, 2016, IEEE Electron Device Letters.

Modeling independent multi-gate MOSFETs

C. Hu, Y. Chauhan, Yen-Kai Lin, 2016 .

Modeling of threshold voltage for operating point using industry standard BSIM-IMG model

C. Hu, Y. Chauhan, Yen-Kai Lin, 2016, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Characterization of RF Noise in UTBB FD-SOI MOSFET

C. Hu, Y. Chauhan, A. Dasgupta, 2016, IEEE Journal of the Electron Devices Society.

BSIM-IMG: Compact model for RF-SOI MOSFETs

Chenming Hu, Pragya Kushwaha, Sourabh Khandelwal, 2015, 2015 73rd Annual Device Research Conference (DRC).

Compact models for sub-22nm MOSFETs

Ali M. Niknejad, Chenming Hu, Yogesh Singh Chauhan, 2011 .

Molybdenum Gate Work Function Engineering for Ultra-Thin-Body Silicon-on-Insulator (UTB SOI) MOSFETs

C. Hu, T. King, P. Ranade, 2003 .

An Extension Of BSIM3 Model Incorporating Velocity Overshoot

Jeffrey Bokor, Michael Orshansky, Chenming Hu, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

The EEPROM as an analog memory drive

Chenming Calvin Hu, Ping-Keung Ko, T.-C. Ong, 1989 .

Errors in threshold-voltage measurements of MOS transistors for dopant-profile determinations

C. Hu, M. Chi, 1981 .

A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides

C. Sodini, C. Hu, T. Ma, 1991, International Electron Devices Meeting 1991 [Technical Digest].

The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films

C. Hu, Ching-Yuan Wu, Liangmei Wu, 1987 .

Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs

C. Hu, Y. Chauhan, S. Dey, 2020, IEEE Transactions on Electron Devices.

Recovery of threshold voltage after hot-carrier stressing

Chenming Hu, T.-C. Ong, C. Hu, 1988 .

An accurate model of thin film SOI-MOSFET breakdown voltage

Ping-Keung Ko, Chenming Hu, P. Cheng, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits

Mansun Chan, Bin Yu, Ping Keung Ko, 1995 .

Investigation of Mo/Ti/AlN/HfO2 High-k Metal Gate Stack for Low Power Consumption InGaAs NMOS Device Application

C. Hu, Yueh-Chin Lin, E. Chang, 2017, IEEE Electron Device Letters.

SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films

Mansun Chan, Ping Keung Ko, Chenming Hu, 1995, Proceedings of International Electron Devices Meeting.

Air spacer MOSFET technology for 20nm node and beyond

Chenming Hu, C. Hu, Jemin Park, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

ULSI-quality gate oxide on thin-film-silicon-on-insulator

C. Hu, C. Hu, M. Racanelli, 1993, Proceedings of IEEE International Electron Devices Meeting.

Characteristics of CMOS devices in high-energy boron-implanted substrates

C. Hu, H. Zappe, 1988 .

GaAs MESFET model for circuit simulation

C. Hu, P. Ko, P. George, 1989 .

Improved Modeling of Bulk Charge Effect for BSIM-BULK Model

C. Hu, Y. Chauhan, H. Agarwal, 2019, IEEE Transactions on Electron Devices.

Modeling and design study of nanocrystal memory devices

Y. King, C. Hu, T. King, 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

Field-realigned nematic-liquid-crystal optical waveguides

C. Hu, J. Whinnery, 1974 .

Flicker noise in advanced CMOS technology: Effects of halo implant

Xin Zhang, Ali M. Niknejad, Samuel Martin, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Enhanced conductivity and breakdown of oxides grown on heavily implanted substrates

Jack C. Lee, C. Hu, C. Hegarty, 1991 .

Oxides grown on textured single-crystal silicon-dependence on process and application of EEPROMs

C. Hu, Y. Fong, A. Wu, 1990 .

Anomalous Subthreshold Behaviors in Negative Capacitance Transistors

C. Hu, D. Kwon, S. Salahuddin, 2020, 2006.02594.

Non-hysteretic negative capacitance FET with Sub- 30mV/dec swing over 106X current range and ION of 0.3mA/μm without strain enhancement at 0.3V VDD

C. Hu, C. Yeung, S. Salahuddin, 2012 .

A two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM

C. Hu, D. Moy, D. Pearson, 1989, Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference.

Quarter-micrometre surface and buried channel PMOSFET modelling for circuit simulation

Bin Yu, C. Hu, M. Jeng, 1996 .

Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC

C. Hu, W. Lo, Kuan-Neng Chen, 2019, 2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

C. Hu, W. Yeh, Kuan-Neng Chen, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Novel 140°C hybrid thin film solar cell/transistor technology with 9.6% conversion efficiency and 1.1 cm2/V-s electron mobility for low-temperature substrates

Jung Y. Huang, C. Hu, C. Pan, 2010, 2010 International Electron Devices Meeting.

Simulating radiation reliability with BERT

Paolo Pavan, Ping Keung Ko, Chenming Hu, 1995 .

Thickness and other effects on oxide and interface damage by plasma processing

Chenming Hu, Hyungcheol Shin, K. Noguchi, 1993, 31st Annual Proceedings Reliability Physics 1993.

EFFECTS OF HIGH ELECTRIC FIELD TRANSIENTS ON THIN GATE OXIDE MOSFETs.

Chenming Hu, C. Hu, Y. Fong, 1987 .

A dynamic depletion SOI MOSFET model for SPICE

Samel K. H. Fung, C. Hu, P. Ko, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models

Yuhua Cheng, Chenming Hu, Kai Chen, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Improvement of Charge Trapping Char act er is tics of N, 0- Annealed and Reoxidized N,O-Annealed Thin Oxides

C. Hu, P. Ko, H. Wann, 1992 .

TOPICAL REVIEW: Thin gate oxide damage due to plasma processing

Chenming Hu, Hyungcheol Shin, C. Hu, 1996 .

PLASMA CHARGING DAMAGE DURING OVER-ETCH TIME OF ALUMINUM

C. Hu, Hyungcheol Shin, Geunsook Park, 1998 .

Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs

C. Hu, S. Salahuddin, Yen-Kai Lin, 2019, IEEE Transactions on Electron Devices.

Compact Modeling for the Changing Transistor (Plenary Paper)

Chenming Hu, C. Hu, 2013 .

AC effects in IC reliability

C. Hu, 1996, Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

BSIM—SPICE Models Enable FinFET and UTB IC Designs

Ali M. Niknejad, Yogesh Singh Chauhan, Chenming Hu, 2013, IEEE Access.

Modeling of GaN-Based Normally-Off FinFET

C. Hu, Y. Chauhan, S. Khandelwal, 2014, IEEE Electron Device Letters.

Separation by plasma implantation of oxygen (SPIMOX) operational phase space

C. Hu, N. Cheung, P. Chu, 1997 .

Separation of plasma implantation of oxygen to form silicon on insulator

C. Hu, N. Cheung, P. Chu, 1997 .

Formation of buried oxide in silicon using separation by plasma implantation of oxygen

C. Hu, N. Cheung, P. Chu, 1995 .

Correction to "Determination of nonuniform diffusion length and electric field in semiconductors"

C. Hu, 1978 .

High performance 0.1 /spl mu/m PD SOI tunneling-biased MOSFETs (TBMOS)

C. Hu, Yu-Lin Chu, Kuo-Nan Yang, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Vivek Subramanian, Jeffrey Bokor, Chenming Hu, 2002 .

Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/

Ya-Chin King, Chenming Hu, Tsu-Jae King, 2001 .

Effect of substrate contact on ESD failure of advanced CMOS integrated circuits

Chenming Hu, C. Hu, Y. Loh, 1993 .

The prospect of process-induced charging damage in future thin gate oxides

C. Hu, Donggun Park, 1999 .

Impact of plasma charging damage and diode protection on scaled thin oxide

C. Hu, Hyungcheol Shin, Zhi-Jian Ma, 1993, Proceedings of IEEE International Electron Devices Meeting.

Dual-metal gate technology for deep-submicron CMOS transistors

Hongfa Luan, Dim-Lee Kwong, Pushkar Ranade, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Molybdenum as a gate electrode for deep sub-micron CMOS technology

Y. Yeo, C. Hu, H. Takeuchi, 2000 .

Transistor Characteristics with TaO Gate Dielectric

Y. King, C. Hu, T. King, 1998 .

Electrical characteristics of ferroelectric PZT thin films for DRAM applications

Chenming Hu, R. Moazzami, C. Hu, 1992 .

Electrical conduction and breakdown in sol-gel derived PZT thin films

C. Hu, R. Moazzami, W. Shepherd, 1990, 28th Annual Proceedings on Reliability Physics Symposium.

On Integrating a Polycide-ONO-Poly Capacitor into a 0.8㎛ Digital Technology for Mixed-Signal ASICs

Chenming Hu, Calvin T. Gabriel, Subhash R. Nariani, 1993 .

Electromigration characteristics of Al/W via contact under unidirectional and bidirectional current conditions

Jiang Tao, Chenming Hu, Nathan W. Cheung, 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

Characterization of contact and via failure under short duration high pulsed current stress

Kaustav Banerjee, A. Amerasekera, Chenming Hu, 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs

Chetan Kumar Dabhi, C. Hu, Y. Chauhan, 2019, 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

C. Hu, Y. Chauhan, A. Niknejad, 2011, 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding.

Deep-Trap Stress Induced Leakage Current Model for Nominal and Weak Oxides

C. Hu, S. Kamohara, T. Okumura, 2008 .

Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node

C. Hu, S. Salahuddin, Joseph Wang, 2019, IEEE Electron Device Letters.

Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS

C. Hu, T. Liu, Chung-Hsun Lin, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Source and Drain Parasitics: Layout-Dependence Model

Chenming Hu, Weidong Liu, C. Hu, 2011 .

On thermal effects in deep sub-micron VLSI interconnects

A. Sangiovanni-Vincentelli, C. Hu, K. Banerjee, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

MOS memory using germanium nanocrystals formed by thermal oxidation of Si/sub 1-x/Ge/sub x/

Y. King, C. Hu, T. King, 1998 .

Ferroelectricity in HfO2 thin films as a function of Zr doping

C. Hu, S. Salahuddin, Sangwan Kim, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Operational phase-space of separation by plasma implantation of oxygen (SPIMOX)

C. Hu, B. Linder, N. Cheung, 1996, Proceedings of 11th International Conference on Ion Implantation Technology.

Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET

Y. Yeo, C. Hu, T. King, 2001 .

A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient

C. Hu, S. Zheng, J. Yue, 1996, Proceedings of 1st International Symposium on Plasma Process-Induced Damage.

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Chenming Hu, Mong-Song Liang, Fu-Liang Yang, 2004, VLSIT 2004.

45nm Node Planar-SO1 Technology with 0.296pm2 6T-SUM Cell

Chenming Hu, Mong-Song Liang, Di-Hong Lee, 2004 .

Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices

C. Hu, Wen-Chin Lee, T. King, 1999 .

Observation of Reduced Boron Penetration and Gate Depletion for Poly-Si Ge Gated PMOS Devices

C. Hu, Wen-Chin Lee, T. King, 1999 .

Performance enhancement in deep-submicron poly-SiGe-gated CMOS devices

C. Hu, Wen-Chin Lee, T. King, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology

Y. King, C. Hu, Wen-Chin Lee, 1998 .

Optimized poly-Si/sub 1-x/Ge/sub x/-gate technology for dual gate CMOS application

C. Hu, Wen-Chin Lee, T. King, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

Gate Engineering for

C. Hu, Wen-Chin Lee, T. King, 1998 .

Investigation of Poly-Si 1 x Ge x for Dual-Gate CMOS Technology

C. Hu, Wen-Chin Lee, 1998 .

Improved Sub-micron Cmos Device Performance Due To Fluorine In Cvd Tungsten Silicide

C. Hu, D. Pramanik, K. Chang, 1991, 1991 Symposium on VLSI Technology.

Reliability of Thin Si02 at Direct-Thnneling Voltages

C. Hu, K. Schuegraf, Dong-gun Park, 1994 .

Characteristics of field effect a-Si:H solar cells

C. Hu, H. Koinuma, H. Fujioka, 1998 .

Electrical Characteristics of n, p-In0.53Ga0.47As MOSCAPs With In Situ PEALD-AlN Interfacial Passivation Layer

C. Hu, S. Salahuddin, Yueh-Chin Lin, 2014, IEEE Transactions on Electron Devices.

Electromigration Reliability in Nanoscale Cu Interconnects

C. Hu, P. Flaitz, L. Gignac, 2007 .

Observation of anti-Stokes fluorescence in organic dye solutions

C. Hu, T. Gustafson, M. S. Chang, 1972 .

2 D-2 D tunneling field-effect transistors using WSe 2 / SnSe 2 heterostructures

C. Hu, A. Javey, M. Hettick, 2016 .

Comparison of Ni-Metal Induced Lateral Crystallization Thin-Film Transistors Fabricated by Rapid Thermal Annealing and Conventional Furnace Annealing at 565 °C

C. Hu, Y. S. Wu, J. Gong, 2007 .

Absorption processes associated with anti‐Stokes fluorescence in rhodamine B solutions

C. Hu, T. Gustafson, M. S. Chang, 1973 .

Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs

Mohit D. Ganeriwala, C. Hu, Y. Chauhan, 2016, IEEE Journal of the Electron Devices Society.

Capacitance Modeling in III–V FinFETs

C. Hu, Y. Chauhan, A. Agarwal, 2015, IEEE Transactions on Electron Devices.

Robust Compact Model of High-Voltage MOSFET’s Drift Region

C. Hu, G. Pahwa, Y. Chauhan, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Competitive Oxidation During Buried Oxide Formation Using Separation by Plasma Implantation of Oxygen (Spimox)

C. Hu, N. Cheung, P. Chu, 1995 .

A novel SOI CBiCMOS compatible device structure for analog and mixed-mode circuits

C. Hu, P. Ko, M. Chan, 1995, 1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings.

Device characteristics of mosfets in MeV implanted substrates

C. Hu, H. Zappe, 1987 .

Patterning sub-30-nm MOSFET gate with i-line lithography

Chenming Hu, Tsu-Jae King, K. Asano, 2001 .

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Yao-Jen Lee, C. Hu, P. Sung, 2014, IEEE Transactions on Electron Devices.

The Berkeley reliability simulator BERT: an IC reliability simulator

Chenming Hu, C. Hu, 1992 .

Circuit reliability simulator for interconnect, via, and contact electromigration

Peng Fang, Chenming Hu, Nathan W. Cheung, 1992 .

Highly crystalline MoS2 thin films grown by pulsed laser deposition

C. Hu, R. Maboudian, L. You, 2015 .

Arsenic‐implanted Si layers annealed using a cw Xe arc lamp

C. Hu, C. Drowley, 1981 .

Novel Ti-SALICIDE process with low resistivity for sub-0.2 /spl mu/m CMOS technology

C. Hu, Qiuxia Xu, 1998, 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105).

New Ti-SALICIDE Process Using Sb and Ge Preamorphization for Sub-0 . 2 m CMOS Technology

C. Hu, Qiuxia Xu, 1998 .

Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology

Chenming Hu, Yee-Chia Yeo, Tsu-Jae King, 2002 .

Berkeley reliability tools-BERT

Elyse Rosenbaum, Ping-Keung Ko, Chenming Hu, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation

Chenming Hu, K. N. Quader, E. R. Minami, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits

Chenming Hu, Peter George, P. K. Ko, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

Substrate hole current and oxide breakdown

Chenming Hu, Stephen E. Holland, C. Hu, 1986 .

Rapid (<5 min) Identification of Pathogen in Human Blood by Electrokinetic Concentration and Surface-Enhanced Raman Spectroscopy

C. Hu, Hsien-Chang Chang, Fu-Liang Yang, 2013, Scientific Reports.

BSIM-CMG 110.0.0: Multi-gate MOSFET compact model: technical manual

Ali M. Niknejad, Chenming Hu, Chung-Hsun Lin, 2014 .

BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations

Ali M. Niknejad, Peter M. Lee, Chenming Hu, 2012 .

Plasma etching antenna effect on oxide-silicon interface reliability

Chenming Hu, Hyungcheol Shin, C. Hu, 1993 .

A physics-based MOSFET noise model for circuit simulators

Ping-Keung Ko, Chenming Hu, K. K. Hung, 1990 .

Single crystal functional oxides on silicon

Asif Islam Khan, Chenming Hu, Long You, 2015, Nature Communications.

MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications

Yee-Chia Yeo, Chenming Hu, Qiang Lu, 2001 .

Topographic measurement of electromigration-induced stress gradients in aluminum conductor lines

Chenming Hu, Ping-Chuan Wang, Ismail C. Noyan, 2000 .

MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations

Chenming Hu, Tsu-Jae King, Yee-Chia Yeo, 2003 .

A Density Metric for Semiconductor Technology [Point of View]

H.-S. Philip Wong, Jeffrey Bokor, James D. Plummer, 2020, Proc. IEEE.

Real-time x-ray microbeam characterization of electromigration effects in Al(Cu) wires

J. Jordan-Sweet, C. Hu, Ping-Chuan Wang, 2001 .

Negative Capacitance Enables FinFET Scaling Beyond 3nm Node

C. Hu, S. Salahuddin, A. Dasgupta, 2020, 2007.14448.

FinFET scaling to 10 nm gate length

Bin Yu, Haihong Wang, Qi Xiang, 2002, Digest. International Electron Devices Meeting,.

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era

Chenming Hu, Tsu-Jae King, C. Hu, 2002 .

Ultra Thin Body Silicon-On-Insulator (UTB SOI) MOSFET with Metal Gate Work-function Engineering for sub-70 nm Technology Node

Pushkar Ranade, Chenming Hu, Tsu-Jae King, 2002 .

35 nm CMOS FinFETs

Yang-Kyu Choi, Chenming Hu, Mong-Song Liang, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Sub-20 nm CMOS FinFET technologies

Chenming Hu, N. Lindert, Tsu-Jae King, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain

Chenming Hu, Tsu-Jae King, Daewon Ha, 2001 .

Gate length scaling and threshold voltage control of double-gate MOSFETs

Jeffrey Bokor, Chenming Hu, Leland Chang, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Gate-induced band-to-band tunneling leakage current in LDD MOSFETs

Chenming Hu, P. K. Ko, C. Hu, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs

Kun-Ming Chen, G. Huang, C. Hu, 2019, International Electron Devices Meeting.

S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

C. Hu, P. Su, Shih-En Huang, 2021, IEEE Transactions on Electron Devices.

Sub-60mV-swing negative-capacitance FinFET without hysteresis

Chenming Hu, Sayeef Salahuddin, Kai-Shin Li, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A 0.1-/spl mu/m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy

Chenming Hu, K. Noda, T. Uchida, 1998 .

Planarized Copper Interconnects by Selective Electroless Plating

Jiang Tao, Chenming Hu, Nathan W. Cheung, 1992 .

Modern Semiconductor Devices for Integrated Circuits

Chenming Calvin Hu, C. Hu, 2009 .

Determination of diffusion length and surface recombination velocity by light excitation

C. Hu, C. Drowley, 1978 .

MOS capacitance measurements for high-leakage thin dielectrics

Chenming Hu, C. Hu, K. Yang, 1999 .

Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density

G. Huang, C. Hu, Tahui Wang, 2012, IEEE Electron Device Letters.

The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability

Ping-Keung Ko, Chenming Hu, Jone-Fang Chen, 1991 .

LED charge-control model and speed at high currents

C. Hu, 1978 .

BSIM4 and MOSFET Modeling For IC Simulation

Weidong Liu, Chenming Hu, C. Hu, 2011, International Series on Advances in Solid State Electronics and Technology.

Thermal Stability of Copper Contact Metallization Using Ru-Containing Liner

C. Hu, B. Haran, D. Canaperi, 2011 .

Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles

C. Hu, S. Salahuddin, J. Bae, 2021, IEEE Electron Device Letters.

Effects of Annealing on Ferroelectric Hafnium–Zirconium–Oxide-Based Transistor Technology

C. Hu, C. Su, Tian-Li Wu, 2019, IEEE Electron Device Letters.

Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery

Chenming Hu, Sayeef Salahuddin, Ava J. Tan, 2017, IEEE Electron Device Letters.

Role of electrode-induced oxygen vacancies in regulating polarization wake-up in ferroelectric capacitors

C. Hu, Y. Tseng, Yi-Jan Lin, 2020 .

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Kurt Keutzer, Linda S. Milor, Michael Orshansky, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Compact models of negative-capacitance FinFETs: Lumped and distributed charge models

Chenming Hu, Sayeef Salahuddin, Sourabh Khandelwal, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Chenming Hu, Yogesh Singh Chauhan, Sayeef Salahuddin, 2016, IEEE Transactions on Electron Devices.

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation

Chenming Hu, Yogesh Singh Chauhan, Sayeef Salahuddin, 2016, IEEE Transactions on Electron Devices.

Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics

Chenming Hu, Sayeef Salahuddin, Sourabh Khandelwal, 2017, IEEE Electron Device Letters.

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Asif Islam Khan, Chenming Hu, Sayeef Salahuddin, 2016, IEEE Electron Device Letters.

Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

C. Hu, S. Salahuddin, Yen-Kai Lin, 2019, IEEE Electron Device Letters.

Design of Negative Capacitance Field-Effect Transistor

C. Hu, M. Kao, 2020 .

Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel

C. Hu, S. Salahuddin, Yen-Kai Lin, 2019, IEEE Electron Device Letters.

Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

C. Hu, A. Sachid, S. Salahuddin, 2018, IEEE Transactions on Electron Devices.

Plasma etching charge-up damage to thin oxides

Chenming Hu, Hyungcheol Shin, Graham W. Hills, 1993 .

High current effects in silicide films for sub-0.25 μm VLSI technologies

J. Kittl, C. Hu, K. Banerjee, 1998 .

Chapter 3 - Hot-Carrier Effects

Chenming Hu, C. Hu, 1989 .

Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing

C. Hu, C. Su, Tian-Li Wu, 2020, IEEE Transactions on Electron Devices.

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Yu Cao, Dennis Sylvester, Chenming Hu, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Design Optimization Techniques in Nanosheet Transistor for RF Applications

C. Hu, S. Salahuddin, A. Dasgupta, 2020, IEEE Transactions on Electron Devices.

BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs

C. Hu, Y. Chauhan, S. Salahuddin, 2020, IEEE Transactions on Electron Devices.

Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Yu Cao, Shen Lin, Chenming Hu, 2002, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

RLC signal integrity analysis of high-speed global interconnects [CMOS]

Yu Cao, Dennis Sylvester, Chenming Hu, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Effects of global interconnect optimizations on performance estimation of deep submicron design

Yu Cao, Dennis Sylvester, Andrew B. Kahng, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Performance and Vdd scaling in deep submicrometer CMOS

Chenming Hu, C. Hu, Kai Chen, 1998, IEEE J. Solid State Circuits.

Negative capacitance enables GAA scaling VDD to 0.5 V

C. Hu, S. Salahuddin, M. Kao, 2021, Solid-State Electronics.

Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

Asif Islam Khan, Chenming Hu, Sayeef Salahuddin, 2016, IEEE Transactions on Electron Devices.

Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)

C. Hu, V. Hu, Yen-Kai Lin, 2020, IEEE Transactions on Electron Devices.

Polarity asymmetry of oxides grown on polycrystalline silicon

Chenming Hu, Jack C. Lee, C. Hu, 1988 .

Quantum yield of electron impact ionization in silicon

Robert W. Brodersen, Chenming Hu, C. Hu, 1985 .

Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology]

Chenming Hu, Wen-Chin Lee, C. Hu, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Optimum doping profile for minimum ohmic resistance and high-breakdown voltage

Chenming Hu, C. Hu, 1979 .

Introductory invited paper The prospect of process-induced charging damage in future thin gate oxides

C. Hu, Donggun Park, 1999 .

Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer

Chenming Calvin Hu, Sayeef Salahuddin, Edward Yi Chang, 2014, IEEE Electron Device Letters.

Efficient gate oxide defect screen for VLSI reliability

Chenming Hu, W. Y. Chan, C. Hu, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Two-dimensional to three-dimensional tunneling in InAs/AlSb/GaSb quantum well heterojunctions

C. Hu, A. Javey, R. Kapadia, 2013 .

Characterization and modeling of electromigration failures in multilayered interconnects and barrier layer materials

C. Hu, N. Cheung, J. Tao, 1996 .

Ion-cut silicon-on-insulator fabrication with plasma immersion ion implantation

Chenming Hu, Nathan W. Cheung, Jing Min, 1997 .

Reliability of thin SiO2

Chenming Hu, K. F. Schuegraf, C. Hu, 1994 .

Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack

C. Hu, D. Kwon, S. Salahuddin, 2020, IEEE Electron Device Letters.

Low power negative capacitance FETs for future quantum-well body technology

Chenming Hu, Chun Wing Yeung, S. Salahuddin, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal–Oxide–Semiconductor Field-Effect Transistors

C. Hu, Yueh-Chin Lin, E. Chang, 2016, IEEE Electron Device Letters.

Improved MOSFET electron mobility model for advanced gate dielectric stacks

Kevin J. Yang, C. Hu, T. King, 2002, 60th DRC. Conference Digest Device Research Conference.

Modeling Advanced FET Technology in a Compact Model

Chenming Hu, Chung-Hsun Lin, Xuemei Xi, 2006, IEEE Transactions on Electron Devices.

Ultra‐large‐scale integration device scaling and reliability

Chenming Hu, C. Hu, 1994 .

Gate engineering for deep-submicron CMOS transistors

Chenming Hu, Tsu-Jae King, Wen-Chin Lee, 1998 .

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

C. Hu, J. Kedzierski, E. Anderson, 2000 .

Stabilization of ferroelectric phase in tungsten capped Hf0.8Zr0.2O2

C. Hu, S. Salahuddin, A. Yadav, 2017 .

Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics

Y. Yeo, C. Hu, T. King, 2001 .

Hot-carrier reliability of p-MOSFET with ultra-thin silicon nitride gate dielectric

Y. Yeo, C. Hu, T. King, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response

C. Hu, G. Luo, Fu-Liang Yang, 2010, 2010 International Electron Devices Meeting.

Green transistor as a solution to the IC power crisis

Chenming Hu, C. Hu, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Green Transistor - A VDD Scaling Path for Future Low Power ICs

Chenming Hu, D. Chou, P. Patel, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

A Compact Model of Antiferroelectric Capacitor

C. Hu, S. Salahuddin, Chien-Ting Tung, 2022, IEEE Electron Device Letters.

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

Chenming Hu, Pragya Kushwaha, Yogesh Singh Chauhan, 2016, IEEE Transactions on Microwave Theory and Techniques.

Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology

C. Hu, T. King, D. Ju, 1997 .

Polysilicon gate depletion effect on IC performance

C. Hu, P. Ko, M. Chan, 1995 .

Liquid-crystal waveguides for integrated optics

Chenming Hu, John R. Whinnery, C. Hu, 1977 .

Losses of a nematic liquid-crystal optical waveguide*

Chenming Hu, John R. Whinnery, C. Hu, 1974 .

Noise modeling and characterization for 1.5-V 1.8-GHz SOI low-noise amplifier

Wei Jin, Chenming Hu, Weidong Liu, 2001 .

Nearly defect-free Ge gate-all-around FETs on Si substrates

C. Hu, P. Sung, G. Luo, 2011, 2011 International Electron Devices Meeting.

New analysis of a high‐voltage vertical multijunction solar cell

C. Hu, R. Frank, J. Carney, 1977 .

Optical second‐harmonic reflection from polycrystalline silicon and its relation to grain boundaries

G. P. Li, C. Hu, Y. Hua, 1994 .

A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation

Ping Keung Ko, Chenming Hu, C. Hu, 1997 .

Tunnel Field Effect Transistor With Raised Germanium Source

Tsu-Jae King Liu, Sung Hwan Kim, Chenming Hu, 2010, IEEE Electron Device Letters.

Suppressing Non-Uniform Tunneling in InAs/GaSb TFET With Dual-Metal Gate

Chun-Yen Chang, C. Hu, E. Chang, 2016, IEEE Journal of the Electron Devices Society.

Spacer Engineering in Negative Capacitance FinFETs

C. Hu, S. Salahuddin, Yen-Kai Lin, 2019, IEEE Electron Device Letters.

Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors

C. Hu, D. Kwon, S. Salahuddin, 2019, IEEE Electron Device Letters.

Programming characteristics of the steep turn-on/off feedback FET (FBFET)

Tsu-Jae King Liu, Chenming Hu, A. Padilla, 2006, 2009 Symposium on VLSI Technology.

Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm

Chang Yong Kang, Hsing-Huang Tseng, Raj Jammy, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction

C. Hu, G. Pahwa, S. Salahuddin, 2022, IEEE Transactions on Electron Devices.

Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation

Y. King, C. Hu, C. Kuo, 2001 .

A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET

Chenming Hu, Pin Su, Wei-Xiang You, 2020, IEEE Journal of the Electron Devices Society.

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Toshihiro Sugii, Chenming Hu, N. Lindert, 1999, IEEE J. Solid State Circuits.

Circuit Reliability Simulation

C. Hu, 1995 .

Circuit-level simulation of TDDB failure in digital CMOS circuits

Elyse Rosenbaum, Ping-Keung Ko, Chenming Hu, 1995 .

Reliability of thin SiO/sub 2/ at direct-tunneling voltages

Donggun Park, Chenming Hu, K. F. Schuegraf, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

ccelerated Testing of Si02 Reliability

C. Hu, E. Rosenbaum, J. King, 1996 .

Monitoring plasma-process induced damage in thin oxide

Chenming Hu, Hyungcheol Shin, C. Hu, 1993 .

Reliability Issues of MOS and Bipolar ICs (Invited Paper)

Chenming Hu, C. Hu, 1989 .

Low-pressure chemical vapor deposited oxide process for MOS device application.

Jack C. Lee, C. Hu, 1988 .

Negative capacitance enables FinFET and FDSOI scaling to 2 nm node

Vita Pi-Ho Hu, Chenming Hu, Angada B. Sachid, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation

Elyse Rosenbaum, Ping Keung Ko, Chenming Hu, 1993 .

Hot-carrier-induced degradation of metal-oxide-semiconductor field-effect transistors: Oxide charge versus interface traps

Jeong Yeol Choi, Ping Keung Ko, Chenming Hu, 1989 .

Modeling of nonlinear thermal resistance in FinFETs

Chenming Hu, Pragya Kushwaha, Yogesh Singh Chauhan, 2016 .

Differential voltage amplification from ferroelectric negative capacitance

Michael Hoffmann, Sayeef Salahuddin, Ramamoorthy Ramesh, 2017, 1709.10451.

Multi-Gate MOSFET Compact Model BSIM-MG

Ali M. Niknejad, Chenming Hu, Darsen D. Lu, 2010 .

A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation

Ali M. Niknejad, Pin Su, Mansun Chan, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Excess hot-carrier currents in SOI MOSFETs and its implications

C. Hu, P. Su, K. Goto, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

Mansun Chan, Yuhua Cheng, Jianhui Huang, 1997 .

FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard

Yogesh Singh Chauhan, Sourabh Khandelwal, Chenming Hu, 2015 .

Compact modeling for the changing transistor

Chenming Hu, C. Hu, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

BSIM—making the first international standard MOSFET model

ChenMing Hu, C. Hu, 2008, Science in China Series F: Information Sciences.

Effect of Fluorine Incorporation on 1/f Noise of HfSiON FETs for Future Mixed-Signal CMOS

Chenming Hu, C. Hu, Y. Yasuda, 2006, 2006 International Electron Devices Meeting.

New insight into high-field mobility enhancement of nitrided-oxide N-MOSFET's based on noise measurement

Ping-Keung Ko, Chenming Hu, C. Hu, 1994 .

Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs

Chenming Hu, Pragya Kushwaha, Yogesh Singh Chauhan, 2016 .

Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON

Chenming Hu, C. Hu, T. Liu, 2008, IEEE Transactions on Electron Devices.

Future CMOS scaling and reliability

Chenming Hu, C. Hu, 1993, Proc. IEEE.

0.2V adiabatic NC-FinFET with 0.6mA/µm ION and 0.1nA/µm IOFF

Asif Khan, Chenming Hu, Sayeef Salahuddin, 2015, 2015 73rd Annual Device Research Conference (DRC).

Piezoelectricity-Induced Schottky Barrier Height Variations in AlGaN/GaN High Electron Mobility Transistors

C. Hu, Liwei Lin, F. Sammoura, 2015, IEEE Electron Device Letters.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Ali M. Niknejad, Christian C. Enz, Chenming Hu, 2014, IEEE Transactions on Electron Devices.

BSIM6: Symmetric Bulk MOSFET Model

Ali M. Niknejad, Chenming Hu, Yogesh Singh Chauhan, 2012 .

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels

G. Huang, C. Hu, F. Hou, 2012, 2012 International Electron Devices Meeting.

5nm-gate nanowire FinFET

Chenming Hu, Yee-Chia Yeo, Mong-Song Liang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate

Chenming Hu, Tsu-Jae King, Wen-Chin Lee, 1999 .

Oxide Breakdown Model For Very Low Voltages

Chenming Hu, K. F. Schuegraf, C. Hu, 1993, Symposium 1993 on VLSI Technology.

Impact of AlN Interfacial Dipole on Effective Work Function of Ni and Band Alignment of Ni/HfO2/In0.53Ga0.47As Gate-Stack

C. Hu, Yueh-Chin Lin, E. Chang, 2015, IEEE Transactions on Electron Devices.

Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation

Chenming Hu, S. Rzepka, Kaustav Banerjee, 1998 .

Interfacial layer reduction and high permittivity tetragonal ZrO2 on germanium reaching ultrathin 0.39 nm equivalent oxide thickness

C. Hu, Hung-Chih Chang, Cheewee Liu, 2013 .

Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium

Supika Mashiro, Chenming Hu, Yee-Chia Yeo, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Compact models for real device effects in FinFETs: Quantum-mechanical confinement and double junctions in FinFETs

Ali M. Niknejad, Chenming Hu, Sriramkumar Venugopalan, 2012 .

Solar cells : from basics to advanced systems

Chenming Calvin Hu, Richard M. White, C. Hu, 2012 .

Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling

C. Hu, H. Kam, M. Kao, 2022, IEEE Electron Device Letters.

In0.53Ga0.47As FinFET and GAA-FET With Remote-Plasma Treatment

C. Hu, Yueh-Chin Lin, E. Chang, 2018, IEEE Electron Device Letters.

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Xuemei Xi, Chung-Kai Lin, Ke-Wei Su, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

C. Hu, G. Pahwa, S. Salahuddin, 2021, IEEE Transactions on Electron Devices.

Response Speed of Negative Capacitance FinFETs

Zoran Krivokapic, Chenming Hu, Sayeef Salahuddin, 2018, 2018 IEEE Symposium on VLSI Technology.

FinFET modeling for IC simulation and design

Yogesh Singh Chauhan, Chenming Hu, Darsen D. Lu, 2015 .

A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS2 FET

C. Hu, W. Yeh, Tahui Wang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Impact of Nitrogen ( N ) Implantation into Polysilicon Gate on High-Performance Dual-Gate CMOS Transistors

C. Hu, N. Kepler, B. Yu, 1998 .

Electron trapping in very thin thermal silicon dioxides

Chenming Hu, Mong-Song Liang, C. Hu, 1981, 1981 International Electron Devices Meeting.

A Predictive Tunnel FET Compact Model With Atomistic Simulation Validation

Chenming Hu, Sayeef Salahuddin, Sourabh Khandelwal, 2017, IEEE Transactions on Electron Devices.

Carrier recombination through donors/acceptors in heavily doped silicon

C. Hu, W. Oldham, 1979 .

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

Jeffrey Bokor, Ping-Keung Ko, Chenming Hu, 1997 .

Oscillations during inductive turn-off in rectifiers

D. O. Pederson, Chenming Hu, C. Hu, 1999 .

Non-volatile memory device with true CMOS compatibility

P. Francis, Chenming Hu, L. Chang, 1999 .

MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability

Jia-Min Shieh, Yu-Lun Chueh, Chenming Hu, 2016, 2016 IEEE Symposium on VLSI Technology.

Sub 50-nm FinFET: PMOS

Chenming Hu, Tsu-Jae King, Xuejue Huang, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

BSIM-CMG: Standard FinFET compact model for advanced circuit design

Pragya Kushwaha, Yogesh Singh Chauhan, Chenming Hu, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

BSIM-IMG: A Turnkey compact model for fully depleted technologies

Chenming Hu, C. Hu, Y. Chauhan, 2012, 2012 IEEE International SOI Conference (SOI).

Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity

C. Hu, A. Dasgupta, 2020, IEEE Electron Device Letters.

Compact Model for Geometry Dependent Mobility in Nanosheet FETs

C. Hu, Y. Chauhan, A. Dasgupta, 2020, IEEE Electron Device Letters.

Bulk FinFET With Low- $\kappa $ Spacers for Continued Scaling

C. Hu, A. Sachid, Min-Cheng Chen, 2017, IEEE Transactions on Electron Devices.

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Yu Cao, Dennis Sylvester, Takashi Sato, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

C. Hu, A. Sachid, Chun-Chi Chen, 2017, IEEE Electron Device Letters.

Design of FinFET SRAM Cells Using a Statistical Compact Model

Ali M. Niknejad, Chenming Hu, Chung-Hsun Lin, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

Chenming Hu, Pin Su, Wei-Xiang You, 2019, IEEE Transactions on Electron Devices.

3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration

C. Hu, C. Pan, Fu-Liang Yang, 2012, 2012 International Electron Devices Meeting.

Metal-oxide-semiconductor field-effect-transistor substrate current during Fowler-Nordheim tunneling stress and silicon dioxide reliability

C. Hu, Klaus F. Schuegrafa, 1999 .

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

C. Hu, D. Kwon, S. Salahuddin, 2021, IEEE Transactions on Electron Devices.

Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET

C. Hu, G. Pahwa, S. Salahuddin, 2020, IEEE Transactions on Electron Devices.

Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

Jia-Min Shieh, Kuei-Shu Chang-Liao, Ci-Ling Pan, 2013, 2013 IEEE International Electron Devices Meeting.

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Jia-Min Shieh, Chenming Hu, Wen-Cheng Chiu, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Chenming Hu, A. B. Sachid, C. Hu, 2012, 2012 IEEE International SOI Conference (SOI).

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

Hong Zhou, Chenming Hu, Sayeef Salahuddin, 2018, 2018 IEEE Symposium on VLSI Technology.

FinFET With High- $\kappa $ Spacers for Improved Drive Current

Chenming Hu, Angada B. Sachid, C. Hu, 2016, IEEE Electron Device Letters.

3D FinFET and other sub-22nm transistors

Chenming Hu, C. Hu, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

A Compact Model of Polycrystalline Ferroelectric Capacitor

C. Hu, G. Pahwa, S. Salahuddin, 2021, IEEE Transactions on Electron Devices.

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Yao-Jen Lee, C. Hu, W. Yeh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

Yao-Jen Lee, C. Hu, P. Sung, 2012, 2012 International Electron Devices Meeting.

2D layered materials: From materials properties to device applications

C. Hu, A. Javey, A. Sachid, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Frequency-independent equivalent circuit model for on-chip spiral inductors

Yu Cao, Xuejue Huang, Tsu-Jae King, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs

Chenming Hu, Sayeef Salahuddin, Chun Wing Yeung, 2013, 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Chenming Hu, ChiaHua Ho, Yi-Ping Hsieh, 2013, 2013 Symposium on VLSI Technology.

Thin-body FinFET as scalable low voltage transistor

Chenming Hu, C. Hu, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Ultra-thin body PMOSFETs with selectively deposited Ge source/drain

Chenming Hu, Tsu-Jae King, Daewon Ha, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Moore's law lives on [CMOS transistors]

Jeffrey Bokor, Leland Chang, N. Lindert, 2003 .

A versatile, SOI BiCMOS technology with complementary lateral BJT's

Chenming Hu, S. Parke, F. Assaderaghi, 1992, 1992 International Technical Digest on Electron Devices Meeting.

High field-effect performance and intrinsic scattering in the two-dimensional MoS2 semiconductors

C. Hu, T. Taniguchi, W. Jian, 2021 .

Room temperature observation of velocity overshoot in silicon inversion layers

C. Hu, P. Ko, F. Assaderaghi, 1993, Proceedings of 1993 IEEE International SOI Conference.

SPICE macro model for the simulation of zener diode current-voltage characteristics

Shu-Park Chan, Silphy Wong, Chenmin Hu, 1991 .

Plasma Enhanced Atomic Layer Deposition Passivated HfO2/AlN/In0.53Ga0.47As MOSCAPs With Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density

C. Hu, Yueh-Chin Lin, E. Chang, 2015, IEEE Electron Device Letters.

Hot-carrier reliability design guidelines for CMOS logic circuits

Wei-Jen Huang, Chenming Hu, C. Hu, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation

Peng Fang, Chenming Hu, K. N. Quader, 1994 .

Simulation of MOSFET lifetime under AC hot-electron stress

Jeong Yeol Choi, Chenming Hu, K. Seki, 1988 .

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

Chenming Hu, Sang Lam, M. Chan, 2003, IEEE Electron Device Letters.

A simple subcircuit extension of the BSIM3v3 model for CMOS RF design

Chenming Hu, Suet Fong Tin, K. Mayaram, 2000, IEEE Journal of Solid-State Circuits.

Recent Developments in BSIM for CMOS RF ac and Noise Modeling

Paul R. Gray, Xiaodong Jin, Jeffrey J. Ou, 1999 .

Optical deflection in thin-film nematic-liquid-crystal waveguides

C. Hu, J. Whinnery, N. Amer, 1974 .

Optimum doping profile of power MOSFET epitaxial layer

Chenming Hu, C. Hu, Xingbi Chen, 1982 .

Some issues of power MOSFETs

Chenming Hu, Min-hwa Chi, C. Hu, 1982, 1982 IEEE Power Electronics Specialists conference.

Spacer FinFET: nano-scale CMOS technology for the terabit era

Chenming Hu, Tsu-Jae King, C. Hu, 2001, 2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497).

A charge sheet capacitance model of short channel MOSFETs for SPICE

Hong June Park, Chenming Hu, Ping K. Ko, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Excess noise in GaAs avalanche photodiodes with thin multiplication regions

C. Hu, J. Campbell, B. Streetman, 1997 .

Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits

Kurt Keutzer, Linda S. Milor, Michael Orshansky, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Liquid crystals in integrated optics

C. Hu, J. Whinnery, N. Amer, 1973 .

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

C. Hu, A. Javey, A. Sachid, 2015, IEEE Transactions on Nanotechnology.

SOI thermal impedance extraction methodology and its significance for circuit simulation

Chenming Hu, Philip C. H. Chan, Weidong Liu, 2001 .

SOI MOSFET thermal conductance and its geometry dependence

Chenming Hu, C. Hu, H. Nakayama, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors

C. Hu, D. Kwon, S. Salahuddin, 2020, IEEE Electron Device Letters.

A capacitorless DRAM cell on SOI substrate

Chenming Hu, Hsing-Jen Wann, C. Hu, 1993, Proceedings of IEEE International Electron Devices Meeting.

Challenges in Compact Modeling for RF and Microwave Applications

Ali M. Niknejad, Jin He, Sohrab Emami, 2005 .

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

J.Y.-C. Sun, Chenming Hu, Mong-Song Liang, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Design analysis of thin-body silicide source/drain devices

C. Hu, J. Kedzierski, T. King, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).