M. Chiang

An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

R. F. Tsui, Shien-Yang Wu, C. Y. Lin, 2014, 2014 IEEE International Electron Devices Meeting.

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Shien-Yang Wu, M. Chiang, J. Liaw, 2007, 2007 IEEE International Electron Devices Meeting.

A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2006, 2009 Symposium on VLSI Technology.

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Sreedhar Natarajan, Shien-Yang Wu, Hung-Jen Liao, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

C. O. Chui, M. Chiang, J. Liaw, 2022, 2022 International Electron Devices Meeting (IEDM).

A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

Jonathan Chang, Shien-Yang Wu, Hung-Jen Liao, 2014, IEEE Journal of Solid-State Circuits.

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 16nm FinFET CMOS technology for mobile SoC and computing applications

H. T. Lin, Shien-Yang Wu, T. Miyashita, 2013, 2013 IEEE International Electron Devices Meeting.

Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

Shien-Yang Wu, T. Miyashita, C. H. Tsai, 2016, 2016 IEEE Symposium on VLSI Technology.

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M. Chiang, V. Chang, 2022, 2022 International Electron Devices Meeting (IEDM).