J. Cheng

An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

R. F. Tsui, Shien-Yang Wu, C. Y. Lin, 2014, 2014 IEEE International Electron Devices Meeting.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

A 16nm FinFET CMOS technology for mobile SoC and computing applications

H. T. Lin, Shien-Yang Wu, T. Miyashita, 2013, 2013 IEEE International Electron Devices Meeting.

Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

Shien-Yang Wu, T. Miyashita, C. H. Tsai, 2016, 2016 IEEE Symposium on VLSI Technology.