V. Chang

发表

An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

R. F. Tsui, Shien-Yang Wu, C. Y. Lin, 2014, 2014 IEEE International Electron Devices Meeting.

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Shien-Yang Wu, M. Chiang, J. Liaw, 2007, 2007 IEEE International Electron Devices Meeting.

Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

T. Schram, A. Veloso, M. Jurczak, 2008, 2008 Symposium on VLSI Technology.

32nm gate-first high-k/metal-gate technology for high performance low power applications

J. Liaw, M. Liang, V. Chang, 2008, 2008 IEEE International Electron Devices Meeting.

Demonstration of Metal-Gated Low $V_{t}$ n-MOSFETs Using a Poly-$\hbox{Si/TaN/Dy}_{2}\hbox{O}_{3}/\hbox{SiON}$ Gate Stack With a Scaled EOT Value

T. Schram, C. Adelmann, V. Chang, 2007, IEEE Electron Device Letters.

High performance tantalum carbide metal gate stacks for nMOSFET application

H.J. Lin, H.J. Tao, S.C. Chen, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Effects of plasma-induced damage to ultrathin (/spl les/1.5 nm) gate dielectric on equivalent oxide thickness downscaling using plasma nitridation process

M. Liang, V. Chang, C. C. Chen, 2003, 2003 8th International Symposium Plasma- and Process-Induced Damage..

Direct measurement of gate oxide damage from plasma nitridation process

M. Liang, V. Chang, T. Lee, 2003, 2003 8th International Symposium Plasma- and Process-Induced Damage..

Thermally-Stable High Effective Work Function TaCN and Ta2N Films for pMOS Metal Gate Applications

T. Schram, C. Adelmann, A. Franquet, 2008 .

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

S. Van Elshocht, A. Akheyar, S. Biesemans, 2008, IEEE Electron Device Letters.

A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

C. O. Chui, M. Chiang, J. Liaw, 2022, 2022 International Electron Devices Meeting (IEDM).

Modeling and Engineering of Hafnium Silicate (HfSiO) Gate Dielectrics Deposited by Nano-Laminated Atomic-Layer Deposition (NL-ALD)

M. Liang, V. Chang, C. C. Chen, 2006 .

Effects of $\hbox{Al}_{2}\hbox{O}_{3}$ Dielectric Cap and Nitridation on Device Performance, Scalability, and Reliability for Advanced High- $\kappa$/Metal Gate pMOSFET Applications

T. Schram, V. Chang, L. Ragnarsson, 2007, IEEE Transactions on Electron Devices.

A 16nm FinFET CMOS technology for mobile SoC and computing applications

H. T. Lin, Shien-Yang Wu, T. Miyashita, 2013, 2013 IEEE International Electron Devices Meeting.

Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

Shien-Yang Wu, T. Miyashita, C. H. Tsai, 2016, 2016 IEEE Symposium on VLSI Technology.

Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node

Vincent S. Chang, S.H. Wang, J.H. Lu, 2020, 2020 IEEE Symposium on VLSI Technology.

I/O device optimization techniques tailored for highly-scaled FinFET technology

V. Chang, Chia-Cheng Chen, Hou-Yu Chen, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M. Chiang, V. Chang, 2022, 2022 International Electron Devices Meeting (IEDM).

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

T. Schram, J. Swerts, V. Chang, 2007, IEEE Electron Device Letters.

Experimental Analysis of Quasi-Ballistic Transport in Advanced Si ${n}$ FinFETs Using New Extraction Method

V. Chang, P. Su, Hou-Yu Chen, 2018, IEEE Electron Device Letters.