T. Yamamoto

发表

An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

R. F. Tsui, Shien-Yang Wu, C. Y. Lin, 2014, 2014 IEEE International Electron Devices Meeting.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

N. Horiguchi, T. Yamamoto, S. Satoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

K. Yamaguchi, T. Yamamoto, T. Mogami, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Self-consistent full-band Monte Carlo device simulation for strained nMOSFETs incorporating vertical quantization, multi-subband, and different channel orientation effects

T. Yamamoto, M. Hane, T. Ezaki, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

Y. Tsunashima, T. Yamamoto, H. Ishiuchi, 2002, Digest. International Electron Devices Meeting,.

DE2/AMD1-2:Low Power Consumption TFT-LCD with 4-bit Dynamic Memories Embedded in Each Pixel(Report on AD/IDW'01)

Hidetada Tokioka, Hiroyuki Murai, Mitsuo Inoue, 2001 .

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

A. Ogura, H. Wakabayashi, T. Mogami, 2003, IEEE International Electron Devices Meeting 2003.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

A new degradation scheme for direct-tunneling ultrathin gate dielectric

T. Yamamoto, T. Mogami, N. Kimizuka, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

H. Kitamura, H. Kawamoto, T. Yamamoto, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

H. Kawaura, H. Wakabayashi, M. Hane, 2006, IEEE Transactions on Electron Devices.

A high-performance 0.1 /spl mu/m CMOS with elevated salicide using novel Si-SEG process

T. Tamura, H. Wakabayashi, K. Tokunaga, 1997, International Electron Devices Meeting. IEDM Technical Digest.

An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layer

T. Yamamoto, T. Kunio, K. Yoshida, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

First Quantitative Observation of Local Temperature Fluctuation in Millisecond Annealing

S. Satoh, T. Yamamoto, T. Sukegawa, 2007, 2007 15th International Conference on Advanced Thermal Processing of Semiconductors.

Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology

T. Yamamoto, T. Sugii, H. Ohta, 2007, 2007 IEEE Symposium on VLSI Technology.

A robust 65-nm node CMOS technology for wide-range Vdd operation

T. Fukai, T. Tamura, M. Togo, 2003, IEEE International Electron Devices Meeting 2003.

Aggressive design of millisecond annealing junctions for near-scaling-limit bulk CMOS using raised source/drain extensions

T. Yamamoto, T. Nagumo, M. Hane, 2008, 2008 IEEE International Electron Devices Meeting.

18.5L: Late‐News Paper: low power Consumption TFT‐LCD with Dynamic Memory Embedded in Pixels

Hidetada Tokioka, Hiroyuki Murai, Mitsuo Inoue, 2001 .

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

T. Fukai, M. Togo, K. Imai, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A 16nm FinFET CMOS technology for mobile SoC and computing applications

H. T. Lin, Shien-Yang Wu, T. Miyashita, 2013, 2013 IEEE International Electron Devices Meeting.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Low-power embedded ReRAM technology for IoT applications

K. Takeda, H. Sunamura, N. Furutake, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A new degradation mode of scaled p/sup +/ polysilicon gate pMOSFETs induced by bias temperature (BT) instability

T. Yamamoto, T. Mogami, K. Uwasawa, 1995, Proceedings of International Electron Devices Meeting.