T. Lee

An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

R. F. Tsui, Shien-Yang Wu, C. Y. Lin, 2014, 2014 IEEE International Electron Devices Meeting.

Demonstration of scaled Ge p-channel FinFETs integrated on Si

T. Lee, M. Holland, C. Wann, 2012, 2012 International Electron Devices Meeting.

The effects of STI induced mechanical strain on GIDL current in Hf-based and SiON MOSFETs

M. Liang, T. Lee, Y. Fang, 2009 .