M. Tsai

发表

An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

R. F. Tsui, Shien-Yang Wu, C. Y. Lin, 2014, 2014 IEEE International Electron Devices Meeting.

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Shien-Yang Wu, M. Chiang, J. Liaw, 2007, 2007 IEEE International Electron Devices Meeting.

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

M. Liang, M. Tsai, S. Jang, 2002, Digest. International Electron Devices Meeting,.

Device properties in 90 nm and beyond and implications on circuit design

M. Tsai, S.M. Cheng, C.H. Diaz, 2003, IEEE International Electron Devices Meeting 2003.

Comparison of the diffusion barrier properties of chemical-vapor-deposited TaN and sputtered TaN between Cu and Si

M. Tsai, S. Sun, H. Chiu, 1996 .

A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2006, 2009 Symposium on VLSI Technology.

Metalorganic chemical vapor deposition of tantalum nitride by tertbutylimidotris(diethylamido)tantalum for advanced metallization

M. Tsai, S. Sun, H. Chiu, 1995 .

Evaluation of material property requirements and performance of ultra-low dielectric constant insulators for inlaid copper metallization

M. Tsai, J. Wetzel, K. Monnig, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Metal-organic chemical vapor deposition of tantalum nitride barrier layers for ULSI applications

M. Tsai, S. Sun, H. Chiu, 1995 .

Properties of metalorganic chemical vapor deposited tantalum nitride thin films

M. Tsai, S. Sun, H. Chiu, 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

An Efficient Improvement for Barrier Effect of W-filled Contact

M. Tsai, W. Yeh, S. Chen, 1995 .

Comparison of chemical vapor deposition of TiN using tetrakis-diethylamino-titanium and tetrakis-dimethylamino-titanium

M. Tsai, S. Sun, 1994 .

Characterization of Pd-free electroless Co-based cap selectively deposited on Cu surface via borane-based reducing agent

M. Liang, M. Tsai, C. Wan, 2006 .

CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration

M. Liang, M. Tsai, D. Yu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Electromigration reliability of dual damascene Cu/CVD SiOC interconnects

R. Augur, M. Tsai, W. Yeh, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Reliability of dual damascene Cu metallization

Shau-Lin Shue, M. H. Tsai, M. Tsai, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications

Jun He, R. Chen, Geoffrey Yeap, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Improvement of selectivity during diamond growth utilizing a new process

M. Tsai, Chia-Fu Chen, Sheng-Hsiung Chen, 1995 .

A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Relationship between wafer edge design and its ultimate mechanical strength

M. Tsai, W. Yeh, Po-Ying Chen, 2010 .

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

M. Tsai, W. Yeh, Po-Ying Chen, 2010 .

Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

M. Tsai, W. Yeh, Po-Ying Chen, 2009 .

Annealing impact on damascene Cu resistivity and microstructures

J. D. Luttmer, R. Augur, M. Tsai, 2001, 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443).

Line width dependence of copper resistivity

R. H. Havemann, M. Tsai, Qing-Tang Jiang, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

A 90 nm generation copper dual damascene technology with ALD TaN barrier

M. Liang, M. Tsai, C. Hsieh, 2002, Digest. International Electron Devices Meeting,.

Metalorganic chemical vapor deposition of tungsten nitride for advanced metallization

M. Tsai, S. Sun, H. Chiu, 1996 .

The Impact of Strain Technology on FUSI Gate SOI CMOSFET

M. Tsai, W. Yeh, Po-Ying Chen, 2009 .

A 16nm FinFET CMOS technology for mobile SoC and computing applications

H. T. Lin, Shien-Yang Wu, T. Miyashita, 2013, 2013 IEEE International Electron Devices Meeting.

High performance In0.53Ga0.47As FinFETs fabricated on 300 mm Si substrate

K. Y. Lee, Y. Yeo, M. Tsai, 2016, 2016 IEEE Symposium on VLSI Technology.

High performance/reliability Cu interconnect with selective CoWP cap

M.S. Liang, M.H. Tsai, W.S. Shue, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

A new CVD tungsten nitride diffusion barrier for Cu interconnection

S.C. Sun, M.H. Tsai, H.T. Chiu, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.