M. Eller

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

K.-H. Bach, A. Jain, M. Eller, 2007, IEEE Transactions on Semiconductor Manufacturing.

High performance bulk planar 20nm CMOS technology for low power mobile applications

O. Menut, Y. Liu, S. Samavedam, 2012, 2012 Symposium on VLSI Technology (VLSIT).