Bekim Cilku

Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control

Peter P. Puschner, Daniel Prokesch, Bekim Cilku, 2016, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC).

A Memory Arbitration Scheme for Mixed-Criticality Multicore Platforms

P. Puschner, Bekim Cilku, A. Crespo, 2014 .

Towards Temporal and Spatial Isolation in Memory Hierarchies for Mixed-Criticality Systems with Hypervisors

Peter Puschner, Bekim Cilku, P. Puschner, 2013 .

A TDMA-Based arbitration scheme for mixed-criticality multicore platforms

Alfons Crespo, Peter Puschner, Javier Coronel, 2015, 2015 International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP).

A dual-layer bus arbiter for mixed-criticality systems with hypervisors

Peter P. Puschner, Bernhard Frömel, Bekim Cilku, 2014, 2014 12th IEEE International Conference on Industrial Informatics (INDIN).

A Memory Arbitration Scheme for Mixed-Criticality Multicore Platforms

P. Puschner, Bekim Cilku, A. Crespo, 2014 .

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Martin Schoeberl, Peter P. Puschner, Daniel Prokesch, 2017, 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC).

Designing a time predictable memory hierarchy for single-path code

Peter P. Puschner, Bekim Cilku, P. Puschner, 2015, SIGBED.

A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking

Peter P. Puschner, Daniel Prokesch, Bekim Cilku, 2015, 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops.

Aligning single path loops to reduce the number of capacity cache misses

Peter P. Puschner, Roland Kammerer, Bekim Cilku, 2015, SIGBED.