V. Kathail

HPL-PD Architecture Specification:Version 1.1

B. R. Rau, V. Kathail, M. Schlansker, 2000 .

Acceleration of Algebraic Recurrences on Processors with Instruction Level Parallelism

V. Kathail, M. Schlansker, 1993 .

Optimal interpreters for lambda-calculus based functional languages

Vinod Kathail, V. Kathail, 1990 .

Meld scheduling: relaxing scheduling constraints across region boundaries

Vinod Kathail, Santosh G. Abraham, Brian L. Deitrich, 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

Machine-Description Driven Compilers for EPIC and VLIW Processors

B. Ramakrishna Rau, Vinod Kathail, Shail Aditya, 1999, Des. Autom. Embed. Syst..

PICO: Automatically Designing Custom Computers

B. Ramakrishna Rau, Vinod Kathail, Robert Schreiber, 2002, Computer.

Parallelization of Control Recurrences for ILP Processors

Vinod Kathail, Mike Schlansker, Sadun Anik, 1996, International Journal of Parallel Programming.

Elcor's Machine Description System: Version 3.0

B. Ramakrishna Rau, Vinod Kathail, Shail Aditya, 1998 .

Achieving high levels of instruction-level parallelism with reduced hardware complexity

B. Ramakrishna Rau, Vinod Kathail, Richard Johnson, 1997 .

Automated Synthesis of Hardware Process Networks from Sequential C Code

Ed F. Deprettere, Hristo Nikolov, Vinod Kathail, 2008 .

High-level synthesis of nonprogrammable hardware accelerators

Scott A. Mahlke, B. Ramakrishna Rau, Vinod Kathail, 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.