Hiroki Matsutani

发表

A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection

Yang Qin, Hiroki Matsutani, Masaaki Kondo, 2020, 2020 International Conferences on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData) and IEEE Congress on Cybermatics (Cybermatics).

Performance and cost evaluations of on-chip network topologies in FPGAs (リコンフィギャラブルシステム)

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2009 .

Performance Oriented Management System for Reconfigurable Network Appliances

Hiroki Matsutani, R. Wakikawa, J. Murai, 2004 .

A Parametric Study of Packet-Switched FPGA Overlay Networks

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2006 .

Evaluation of a multicore reconfigurable architecture (リコンフィギャラブルシステム)

Hideharu Amano, Hiroki Matsutani, Vu Manh Tuan, 2009 .

On-Device Learning: A Neural Network Based Field-Trainable Edge AI

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2022, ArXiv.

A link removal methodology for application-specific (リコンフィギャラブルシステム)

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2008 .

A Low-Power Fault-Tolerant NoC using Error Correction and Detection Codes

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2010 .

An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning pdf

Hiroki Matsutani, Hirohisa Watanabe, Mineto Tsukada, 2020, 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

Accelerating ODE-Based Neural Networks on Low-Cost FPGAs

Hiroki Matsutani, Hirohisa Watanabe, Hiroki Matsutani, 2021, 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

Accelerating Neural ODE Based CNN Models on Low-Cost FPGAs

Hiroki Matsutani, Hirohisa Watanabe, 2020, 2012.15465.

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2019, IEEE Transactions on Computers.

Skywalk: A Topology for HPC Networks with Low-Delay Switches

Henri Casanova, Hiroki Matsutani, Michihiro Koibuchi, 2014, 2014 IEEE 28th International Parallel and Distributed Processing Symposium.

A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs

Hiroki Matsutani, K. Sugiura, 2021, 2021 International Conference on Field-Programmable Technology (ICFPT).

An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm pdf

Hiroki Matsutani, Keisuke Sugiura, Hiroki Matsutani, 2020, IEICE Trans. Inf. Syst..

P3Net: PointNet-based Path Planning on FPGA

Hiroki Matsutani, K. Sugiura, 2022, 2022 International Conference on Field-Programmable Technology (ICFPT).

Fast Semi-Supervised Anomaly Detection of Drivers’ Behavior using Online Sequential Extreme Learning Machine

Hiroki Matsutani, Hiroki Oikawa, Tomoya Nishida, 2020, 2020 IEEE 23rd International Conference on Intelligent Transportation Systems (ITSC).

k-Optimized Path Routing for High-Throughput Data Center Networks

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2018, 2018 Sixth International Symposium on Computing and Networking (CANDAR).

Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects

Henri Casanova, Hiroki Matsutani, Michihiro Koibuchi, 2015, IEEE Transactions on Parallel and Distributed Systems.

Layout-conscious random topologies for HPC off-chip interconnects

Henri Casanova, Hiroki Matsutani, Michihiro Koibuchi, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

In-switch approximate processing: Delayed tasks management for MapReduce applications

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

A Sequential Concept Drift Detection Method for On-Device Learning on Low-End Edge Devices

Hiroki Matsutani, T. Yamada, 2022, ArXiv.

An Area-Efficient Recurrent Neural Network Core for Unsupervised Time-Series Anomaly Detection

Hiroki Matsutani, Takuya Sakuma, 2021, IEICE Trans. Electron..

Dependable Responsive Multithreaded Processor for distributed real-time systems

Nobuyuki Yamasaki, Takuma Kogo, Hiroki Matsutani, 2012, 2012 IEEE COOL Chips XV.

The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems

Nobuyuki Yamasaki, Hiroki Matsutani, Kazutoshi Suito, 2012, IEEE Micro.

Communication Size Reduction of Federated Learning based on Neural ODE Model

Hiroki Matsutani, Yuto Hoshino, Hiroki Kawakami, 2022, 2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW).

Communication Size Reduction of Federated Learning using Neural ODE Models

Hiroki Matsutani, Yuto Hoshino, Hiroki Kawakami, 2022, 2208.09478.

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LaKe: The Power of In-Network Computing

Hiroki Matsutani, Yuta Tokusashi, Noa Zilberman, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Accelerating Blockchain Transfer System Using FPGA-Based NIC

Hiroki Matsutani, Shin Morishima, Yuta Tokusashi, 2018, 2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom).

An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning

Hiroki Matsutani, Mineto Tsukada, Hirohisa Watanabe, 2020, 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

A Packet Routing using Lightweight Reinforcement Learning Based on Online Sequential Learning

Hiroki Matsutani, Kenji Nemoto, 2022, 2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW).

An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection

Hiroki Matsutani, Takuya Sakuma, Hiroki Matsutani, 2020, 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

A Hardware-Based Caching System on FPGA NIC for Blockchain

Hiroki Matsutani, Shin Morishima, Yuma Sakakibara, 2018, IEICE Trans. Inf. Syst..

An FPGA NIC Based Hardware Caching for Blockchain

Hiroki Matsutani, Yuma Sakakibara, Kohei Nakamura, 2017, HEART.

An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning

Hiroki Matsutani, K. Sugiura, 2023, arXiv.org.

MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories

Hiroki Matsutani, Yuta Tokusashi, Koya Mitsuzuka, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

Prediction router: Yet another low latency on-chip router architecture

Hideharu Amano, Tsutomu Yoshinaga, Hiroki Matsutani, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

Accelerating Blockchain Search of Full Nodes Using GPUs

Hiroki Matsutani, Shin Morishima, Hiroki Matsutani, 2018, 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Tadahiro Kuroda, Hideharu Amano, Junichiro Kadomoto, 2018, Int. J. Netw. Comput..

3D NoC with Inductive-Coupling Links for Building-Block SiPs

Daisuke Sasaki, Tadahiro Kuroda, Hideharu Amano, 2014, IEEE Transactions on Computers.

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Tadahiro Kuroda, Hideharu Amano, Hiroki Matsutani, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A metamorphotic Network-on-Chip for various types of parallel applications

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

An Efficient Path Setup for a Photonic Network-on-Chip

Tsutomu Yoshinaga, Hiroki Matsutani, Hidetsugu Irie, 2010, 2010 First International Conference on Networking and Computing.

Run-time power gating of on-chip routers using look-ahead routing

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2008, 2008 Asia and South Pacific Design Automation Conference.

A case for random shortcut topologies for HPC interconnects

Henri Casanova, Hideharu Amano, D. Frank Hsu, 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

Key-value Store Chip Design for Low Power Consumption

Hideharu Amano, Hiroki Matsutani, Yuta Tokusashi, 2019, 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit pdf

Hiroki Matsutani, Mineto Tsukada, Hiroki Matsutani, 2021, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2010, 2010 IEEE Fifth International Conference on Networking, Architecture, and Storage.

An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs

Hiroki Matsutani, K. Sugiura, 2022, 2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

Designing low‐diameter interconnection networks with multi‐ported host‐switch graphs

Hideharu Amano, Michihiro Koibuchi, Koji Nakano, 2020, Concurr. Comput. Pract. Exp..

Designing High-Performance Interconnection Networks with Host-Switch Graphs

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2019, IEEE Transactions on Parallel and Distributed Systems.

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2017, IEICE Trans. Inf. Syst..

A Case for Uni-directional Network Topologies in Large-Scale Clusters

Henri Casanova, Hideharu Amano, Hiroki Matsutani, 2017, 2017 IEEE International Conference on Cluster Computing (CLUSTER).

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Hideharu Amano, Koji Nakano, Hiroki Matsutani, 2017, 2017 46th International Conference on Parallel Processing (ICPP).

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2017, IEICE Trans. Inf. Syst..

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

High-Bandwidth Low-Latency Approximate Interconnection Networks

Henri Casanova, Hideharu Amano, Hiroki Matsutani, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Optical network technologies for HPC: computer-architects point of view

Hideharu Amano, Shu Namiki, Tomohiro Kudoh, 2016, IEICE Electron. Express.

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2019, IEEE Transactions on Computers.

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks

Ryuta Kawano, Hideharu Amano, Michihiro Koibuchi, 2020, IEICE Trans. Inf. Syst..

Augmenting low-latency HPC network with free-space optical links

Henri Casanova, Hiroki Matsutani, Michihiro Koibuchi, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Three-Dimensional Layout of On-Chip Tree-Based Networks

Hideharu Amano, D. Frank Hsu, Hiroki Matsutani, 2008, 2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008).

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2007, 2007 International Conference on Parallel Processing (ICPP 2007).

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2007, IEEE Transactions on Parallel and Distributed Systems.

ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC

Hiroki Matsutani, Masaaki Kondo, Man Wu, 2022, 2022 IEEE 24th Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys).

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2018, 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

A Lightweight Concept Drift Detection Method for On-Device Learning on Resource-Limited Edge Devices

Hiroki Matsutani, Takeya Yamada, 2023, 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning

Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, 2022, IEEE Micro.

An On-Device Federated Learning Approach for Cooperative Model Update Between Edge Devices

Hiroki Matsutani, Mineto Tsukada, Rei Ito, 2020, IEEE Access.

An On-Device Federated Learning Approach for Cooperative Anomaly Detection

Hiroki Matsutani, Mineto Tsukada, Rei Ito, 2020, ArXiv.

OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2018, Euro-Par Workshops.

An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm

Hiroki Matsutani, K. Sugiura, 2020, IEICE Trans. Inf. Syst..