Masaaki Kondo

发表

A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection

Yang Qin, Hiroki Matsutani, Masaaki Kondo, 2020, 2020 International Conferences on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData) and IEEE Congress on Cybermatics (Cybermatics).

FLAT: a GPU programming framework to provide embedded MPI

Hiroki Honda, Tsutomu Yoshinaga, Hidetsugu Irie, 2012, GPGPU-5.

A Strawman for an HPC PowerStack

Masaaki Kondo, B. Rountree, M. Schulz, 2018 .

A Compiler Cooperative DVFS Technique based on Statistical Learning

Hiroshi Nakamura, Hiroshi Sasaki, Masaaki Kondo, 2006 .

Geyser: Energy-Efficient MIPS CPU Core with Fine-Grained Run-Time Power Gating

Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, 2012 .

Dynamic Optimization for CMP by Efficient Regression Modeling

Hiroshi Nakamura, Hiroshi Sasaki, Masaaki Kondo, 2008 .

Energy-Efficient Scheduler by Statistical Analysis for Linux

Hiroshi Sasaki, Jun Kanai, Hiroshi Nakamura, 2007 .

Analysis and Modeling of Multiprogramming Performance of Chip Multiprocessors focusing on Resource Contentions

Hiroshi Nakamura, Hiroshi Sasaki, Masaaki Kondo, 2007 .

Multi-Objective Resource Scheduling for IoT Systems Using Reinforcement Learning

Masaaki Kondo, Hiroshi Nakamura, Shaswot Shresthamali, 2022, Journal of Low Power Electronics and Applications.

Enabling circuit-switching in modern on-chip networks

Masaaki Kondo, Jinyu Jiao, Yuan He, 2022, Microprocessors and Microsystems.

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code

Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Scalable deep neural network accelerator cores with cubic integration using through chip interface

Hiroshi Nakamura, Hideharu Amano, Jun Ishii, 2017, 2017 International SoC Design Conference (ISOCC).

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores

Hiroshi Nakamura, Hideharu Amano, Jun Ishii, 2017, 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2019, IEEE Transactions on Computers.

The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption

Masaaki Kondo, T. Ichimura, Ryuichi Sakamoto, 2020, International Conference on High Performance Computing in Asia-Pacific Region.

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing

Yuichi Inadomi, Martin Schulz, Koji Inoue, 2015, SC15: International Conference for High Performance Computing, Networking, Storage and Analysis.

Fast Semi-Supervised Anomaly Detection of Drivers’ Behavior using Online Sequential Extreme Learning Machine

Hiroki Matsutani, Hiroki Oikawa, Tomoya Nishida, 2020, 2020 IEEE 23rd International Conference on Intelligent Transportation Systems (ITSC).

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE Micro.

Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS

Hiroshi Nakamura, Hiroshi Sasaki, Masaaki Kondo, 2007, CARN.

An intra-task dvfs technique based on statistical analysis of hardware events

Hiroshi Nakamura, Hiroshi Sasaki, Masaaki Kondo, 2007, CF '07.

Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework

Martin Schulz, Koji Inoue, Barry Rountree, 2017, 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers

Martin Schulz, Koji Inoue, Barry Rountree, 2018, 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Federated Learning-Based Network Intrusion Detection with a Feature Selection Approach

Yang Qin, Masaaki Kondo, 2021, 2021 International Conference on Electrical, Communication, and Computer Engineering (ICECCE).

Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning

Hiroshi Nakamura, Masaaki Kondo, Shaswot Shresthamali, 2017, ACM Trans. Embed. Comput. Syst..

Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems

Yuan He, Yasutaka Wada, Ryuichi Sakamoto, 2021, IEICE transactions on electronics.

MLMG: Multi-Local and Multi-Global Model Aggregation for Federated Learning

Masaaki Kondo, Yang Qin, Yang Qin, 2021, 2021 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events (PerCom Workshops).

Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems

Wei Huang, Yuan He, Masaaki Kondo, 2017, 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Density-Based Data Selection and Management for Edge Computing

Hiroki Oikawa, Masaaki Kondo, Masaaki Kondo, 2021, 2021 IEEE International Conference on Pervasive Computing and Communications (PerCom).

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference

Masaaki Kondo, Shaswot Shresthamali, Yuan He, 2023, ArXiv.

FAWS: Fault-Aware Weight Scheduler for DNN Computations in Heterogeneous and Faulty Hardware

Masaaki Kondo, Shaswot Shresthamali, Yuan He, 2022, 2022 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom).

Empirical Study for Optimization of Power-Performance with On-Chip Memory

Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, 2005, ISHPC.

Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks

Yuan He, Masaaki Kondo, Jinyu Jiao, 2021, 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

Dynamic Processor Throttling for Power Efficient Computations

Hiroshi Nakamura, Masaaki Kondo, Masaaki Kondo, 2004, PACS.

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2019, IEEE Transactions on Computers.

SCIMA-SMP: on-chip memory processor architecture for SMP

Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, 2004, WMPI '04.

Software-controlled on-chip memory for high-performance and low-power computing

Hiroshi Nakamura, Masaaki Kondo, Motonobu Fujita, 2002, CARN.

Software Controlled Reconfigurable On-Chip Memory for High Performance Computing

Hiroshi Nakamura, Taisuke Boku, Masaaki Kondo, 2000, Intelligent Memory Systems.

SCIMA: Software controlled integrated memory architecture for high performance computing

Hiroshi Nakamura, Taisuke Boku, Masaaki Kondo, 2000, Proceedings 2000 International Conference on Computer Design.

SCIMA: a novel architecture for high performance computing

Hiroshi Nakamura, Shuichi Sakai, Taisuke Boku, 1999, Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650).

Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory

Masaaki Kondo, Masaaki KONDO, Shinichi TANAKA, 2002 .

A High Performance Cluster System Design by Adaptie Power Control

Hiroshi Nakamura, Masaaki Kondo, Yoshimichi Ikeda, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector

Hiroki Matsutani, Masaaki Kondo, Mineto Tsukada, 2018, Euro-Par Workshops.