Heung-Jae Cho

发表

Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

Heesang Kim, Byoungchan Oh, Jong-Ho Lee, 2011, IEEE Transactions on Electron Devices.

Highly Reliable and Scalable Tungsten Polymetal Gate Process for Memory Devices Using Low-Temperature Plasma Selective Gate Reoxidation

Heung-Jae Cho, Sung-Wook Park, N. Kwak, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Robust ternary metal gate electrodes for dual gate CMOS devices

Heung-Jae Cho, J. Roh, V. Misra, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs

Hyungcheol Shin, Heung-Jae Cho, Dong Seup Lee, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Extraction of trap energy and location from random telegraph noise in gate leakage current (Ig RTN) of metal–oxide semiconductor field effect transistor (MOSFET)

Hyungcheol Shin, Byung-Gook Park, Heung-Jae Cho, 2010 .

Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

Heung-Jae Cho, K. Lim, Yong Soo Kim, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Observation of Slow Oxide Traps at MOSFETs Having Metal/High-k Gate Dielectric Stack in Accumulation Mode

Byung-Gook Park, Byoungchan Oh, Jong-Ho Lee, 2010, IEEE Transactions on Electron Devices.

Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO2/Si metal–oxide–semiconductor structures

Heung-Jae Cho, J. Roh, K. Lim, 2002 .

Effect of Selective Oxidation Conditions on Defect Generation in Gate Oxide

Heung-Jae Cho, K. Lim, Yong Soo Kim, 2004 .

Characteristics of TaOxNy Gate Dielectric with Improved Thermal Stability

Heung-Jae Cho, J. Roh, J. Park, 2001 .

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal–oxide–semiconductor capacitors

Heung-Jae Cho, K. Lim, J. Park, 2002 .

A novel method for forming gate spacer and its effects on the W/WN/sub x//poly-Si gate stack

Heung-Jae Cho, K. Lim, Yong Soo Kim, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Reliability Characteristics of W / WN / TaO x N y / SiO2 / Si Metal Oxide Semiconductor Capacitors

Heung-Jae Cho, K. Lim, J. Park, 2002 .

Characteristics of n+ polycrystalline-Si/Al2O3/Si metal–oxide– semiconductor structures prepared by atomic layer chemical vapor deposition using Al(CH3)3 and H2O vapor

In-Seok Yeo, Heung-Jae Cho, Dae-Gyu Park, 2001 .

Studies on the interfacial and crystallographic characteristics of Al2O3/SiO2/Si and ZrO2/SiO2/Si stacks

Heung-Jae Cho, M. Kawasaki, K. Lim, 2005 .

Study on Time Constants of Random Telegraph Noise in Gate Leakage Current Through Hot-Carrier Stress Test

Hyungcheol Shin, Byung-Gook Park, Heung-Jae Cho, 2010, IEEE Electron Device Letters.

Effects of TiN Deposition on the Characteristics of W / TiN / SiO2 / Si Metal Oxide Semiconductor Capacitors

Heung-Jae Cho, K. Lim, J. Park, 2001 .

Novel damage-free direct metal gate process using atomic layer deposition

Heung-Jae Cho, Dae-Gyu Park, Kwan-Yong Lim, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Gate-first high-k/metal gate DRAM technology for low power and high performance products

Sung-Joo Hong, Heung-Jae Cho, N. Kwak, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Crystallographic and Interfacial Characterization of Al 2 O 3 and ZrO 2 Dielectric Films Prepared by Atomic Layer Chemical Vapor Deposition on the Si Substrate

Heung-Jae Cho, K. Lim, Dae-gyu Park, 2003 .

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Kwang-Ok Kim, Seung-Chan Moon, Jin-Soo Kim, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..