W. Burleson

发表

High-Performance and Low-Voltage Sense-Amplifier Techniques for sub-90 nm SRAM

M. Sinha, S. Hsu, A. Alvandpour, 2003 .

- 1-SECURING GREEN CARS : IT SECURITY IN NEXT-GENERATION ELECTRIC VEHICLE SYSTEMS

W. Burleson, C. Paar, Andy Rupp, 2009 .

Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering

Tim Güneysu, Christof Paar, Wayne P. Burleson, 2009, CHES.

A 2 GHz 13 . 6 mW 12 x 9 b Multiplier for Energy Efficient FFT Accelerators

S. Hsu, W. Burleson, R. Krishnamurthy, 2005 .

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

Russell Tessier, Wayne P. Burleson, Atul Maheshwari, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analog VLSI for robot path planning

R. Grupen, C. Connolly, W. Burleson, 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.

Balancing security and utility in Medical Devices?

Farinaz Koushanfar, Wayne P. Burleson, Ari Juels, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Pay as you go

Anna Lysyanskaya, W. Burleson, C. Paar, 1980, Nature.

Low-power encodings for global communication in CMOS VLSI

Mircea R. Stan, Wayne P. Burleson, W. Burleson, 1997, IEEE Trans. Very Large Scale Integr. Syst..

4 Reconfigurable Computing and Digital Signal Processing : Past , Present , and Future

W. Burleson, R. Tessier, 2002 .

Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags

Daniel E. Holcomb, W. Burleson, Kevin Fu, 2007 .

Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration

Wayne P. Burleson, Vikram B. Suresh, Vikram B. Suresh, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Review on Thermal related VLSI Design

Advisor, W. Burleson, Sheng Xu, 2006 .

A dynamically reconfigurable adaptive viterbi decoder

Dennis Goeckel, Russell Tessier, Wayne P. Burleson, 2002, FPGA '02.

Wave-pipelining: a Tutorial and Survey of Recent Research 1

F. Klass, W. Burleson, Wentai Liu, 2007 .

The spring scheduling co-processor: a scheduling accelerator

J. Stankovic, W. Burleson, K. Ramamritham, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Proceedings of the First International Workshop on Post Moore ' s Era Supercomputing

J. Cong, J. Shalf, Kazutomo Yoshii, 2016 .

Jitter in deep sub-micron interconnect

Wayne P. Burleson, Sheng Xu, Jinwook Jang, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Quantifying the impact of current-sensing on interconnect delay trends

Wayne Burleson, A. Maheshwari, S. Srinivasaraghavan, 2002, 15th Annual IEEE International ASIC/SOC Conference.

A simulator for general purpose optical arrays

Wayne P. Burleson, Walter B. Marvin, W. Burleson, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Guest Editor's Introduction

Elias S. Manolakos, Wayne P. Burleson, E. Manolakos, 2000, J. VLSI Signal Process..

Local system S 1 Local system S 2 Prover Verifier

J. L. Martinez-Hurtado, W. Burleson, U. Rührmair, 2015 .

2015 IEEE Symposium on Security and Privacy, SP 2015, San Jose, CA, USA, May 17-21, 2015

Peter G. Neumann, Michael Roe, Ulrich Rührmair, 2015, IEEE Symposium on Security and Privacy.

Efficient Power and Timing Side Channels on PUFs

Jan Sölter, Ulrich Rührmair, Farinaz Koushanfar, 2014 .

Input/output complexity of bit-level VLSI array architectures

Louis L. Scharf, Wayne Burleson, L. Scharf, 1989, Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989..

SystemsE cient VLSI for Lempel-Ziv Data Compressionin Wireless Data Communication Networks

W. Burleson, Bongjin Jung, 2007 .

Exploiting Non-Uniform Access Time in Interconnect Sensitive Cache Partitioning

W. Burleson, Christopher Cowell, 2003 .

Redshift: Manipulating Signal Propagation Delay via Continuous-Wave Lasers

W. Burleson, Kevin Fu, T. Sugawara, 2022, IACR Trans. Cryptogr. Hardw. Embed. Syst..

A Tunable Soft-Error Filtering Circuit Based on Programmable-Threshold Inverters

W. Burleson, B. Datta, 2011 .

Recon.gurable Computing and Digital Signal Processing: Past, Present, and Future

Russell Tessier, Wayne Burleson, W. Burleson, 2001 .

Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells

Amir Rahmati, Daniel E. Holcomb, Kevin Fu, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Persistent Clocks for Batteryless Sensing Devices

Amir Rahmati, Daniel E. Holcomb, Kevin Fu, 2016, ACM Trans. Embed. Comput. Syst..

Analog VLSI for robot path planning

Mircea R. Stan, Wayne P. Burleson, Roderic A. Grupen, 1994, J. VLSI Signal Process..

Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions

Zheng Zhou, Wayne P. Burleson, W. Burleson, 1995, 32nd Design Automation Conference.

Distributed control synthesis for data-dependent iterative algorithms

Wayne P. Burleson, Yongjin Jeong, Bongjin Jung, 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

ARREST: an interactive graphic analysis tool for VLSI arrays

Wayne Burleson, Bongjin Jung, W. Burleson, 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.

A VLSI design methodology for distributed arithmetic

Wayne P. Burleson, Louis L. Scharf, L. Scharf, 1991, J. VLSI Signal Process..

Reducing the power consumption in FPGAs with keeping a high performance level

A.D. Garcia G., W.P. Burleson, J.L. Danger, 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

Stealthy dopant-level hardware Trojans: extended version

Christof Paar, Wayne P. Burleson, Francesco Regazzoni, 2013, Journal of Cryptographic Engineering.

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems

Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, 2021, IEEE Micro.

The combined effect of process variations and power supply noise on clock skew and jitter

Giovanni De Micheli, Wayne P. Burleson, Hu Xu, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters

Wayne P. Burleson, Sriram Srinivasan, Ankireddy Nalamalpu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters

Wayne P. Burleson, Ankireddy Nalamalpu, W. Burleson, 2001, ISPD '01.

Differential current-sensing for on-chip interconnects

Atul Maheshwari, Wayne Burleson, W. Burleson, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis

Wayne P. Burleson, Ankireddy Nalamalpu, W. Burleson, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Bus-invert coding for low-power I/O

Mircea R. Stan, Wayne P. Burleson, W. Burleson, 1995, IEEE Trans. Very Large Scale Integr. Syst..

Design challenges for secure implantable medical devices

Kevin Fu, Wayne P. Burleson, Shane S. Clark, 2012, DAC Design Automation Conference 2012.

Invited: Who is the major threat to tomorrow's security? You, the hardware designer

Onur Mutlu, Wayne P. Burleson, Mohit Tiwari, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Efficient Erasable PUFs from Programmable Logic and Memristors

Ulrich Rührmair, Omid Kavehei, Damith Chinthana Ranasinghe, 2018, IACR Cryptol. ePrint Arch..

Power and Timing Side Channels for PUFs and their Efficient Exploitation

Jan Sölter, Ulrich Rührmair, Farinaz Koushanfar, 2013, IACR Cryptol. ePrint Arch..

Voltage Sensor Implementations for Remote Power Attacks on FPGAs

Daniel E. Holcomb, W. Burleson, R. Tessier, 2022, ACM Trans. Reconfigurable Technol. Syst..

Virtual Proofs of Reality and their Physical Implementation

Ulrich Rührmair, Wayne P. Burleson, Xiaolin Xu, 2015, 2015 IEEE Symposium on Security and Privacy.

On design of a highly secure PUF based on non-linear current mirrors

Wayne P. Burleson, Raghavan Kumar, W. Burleson, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

Daniel E. Holcomb, Kevin Fu, Wayne P. Burleson, 2009, IEEE Transactions on Computers.

Efficient Power and Timing Side Channels for Physical Unclonable Functions

Jan Sölter, Ulrich Rührmair, Farinaz Koushanfar, 2014, CHES.

Multicore soft error rate stabilization using adaptive dual modular redundancy

Russell Tessier, Wayne P. Burleson, Jia Zhao, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Wave-pipelining: a tutorial and research survey

W. Liu, Wayne P. Burleson, Fabian Klass, 1998, IEEE Trans. Very Large Scale Integr. Syst..

PUF Modeling Attacks on Simulated and Silicon Data

Srinivas Devadas, Frank Sehnke, Jan Sölter, 2013, IEEE Transactions on Information Forensics and Security.

Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data

Wayne P. Burleson, Raghavan Kumar, W. Burleson, 2015, RFIDSec.

Synchro-tokens: a deterministic GALS methodology for chip-level debug and test

Wayne P. Burleson, Ian G. Harris, Matthew W. Heath, 2005, IEEE Transactions on Computers.

Synchro-tokens: eliminating nondeterminism to enable chip-level test of globally-asynchronous SoC's

I.G. Harris, M.W. Heath, W.P. Burleson, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis

Wayne P. Burleson, Sandip Kundu, Sudarshan Srinivasan, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Reconfigurable Computing for Digital Signal Processing: A Survey

W. Burleson, R. Tessier, 2001, J. VLSI Signal Process..

Dynamically configurable security for SRAM FPGA bitstreams

Lilian Bossuet, Guy Gogniat, Wayne P. Burleson, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Modeling and experimental demonstration of accelerated self-healing techniques

Mircea R. Stan, Wayne P. Burleson, Xinfei Guo, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Low power on-chip thermal sensors based on wires

Wayne P. Burleson, Basab Datta, W. Burleson, 2007, 2007 IFIP International Conference on Very Large Scale Integration.

Wave-pipelining: is it practical?

Wayne P. Burleson, Fabian Klass, Maciej J. Ciesielski, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Targeting tiled architectures in design exploration

Jean Luc Philippe, Lilian Bossuet, Guy Gogniat, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Fully Integrated Biochip Platforms for Advanced Healthcare

Giovanni De Micheli, Wayne P. Burleson, Catherine Dehollain, 2012, Sensors.

A reconfigurable, power-efficient adaptive Viterbi decoder

Dennis Goeckel, Russell Tessier, Wayne P. Burleson, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Detecting Software Theft in Embedded Systems: A Side-Channel Approach

Christof Paar, Wayne P. Burleson, Georg T. Becker, 2012, IEEE Transactions on Information Forensics and Security.

Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters

Russell Tessier, Wayne P. Burleson, Shiting Lu, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing

Wayne P. Burleson, Vikram B. Suresh, Vikram B. Suresh, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs

Daniel E. Holcomb, Russell Tessier, Xiang Li, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems

Wayne P. Burleson, Lang Lin, W. Burleson, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware

Wayne P. Burleson, Ilia Polian, Philipp Jovanovic, 2014, 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography.

TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks

Amir Rahmati, Daniel E. Holcomb, Kevin Fu, 2012, USENIX Security Symposium.

DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification

Amir Rahmati, Daniel E. Holcomb, Kevin Fu, 2012, RFIDSec.

Formal descriptions, semantics and verification of VLSI array processors

Zheng Zhou, Wayne P. Burleson, W. Burleson, 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations

Wayne P. Burleson, Vishak Venkatraman, W. Burleson, 2005, Sixth international symposium on quality electronic design (isqed'05).

Hybrid side-channel/machine-learning attacks on PUFs: A new threat?

Wayne P. Burleson, Xiaolin Xu, W. Burleson, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

VLSI signal processing, IX

Konstantinos Konstantinides, Teresa H. Meng, Wayne Burleson, 1996 .

Low-power Networks-on-Chip: Progress and remaining challenges

Wayne P. Burleson, Greg Sadowski, Mark Buckler, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Stealthy dopant-level hardware Trojans: extended version

Christof Paar, Wayne P. Burleson, Francesco Regazzoni, 2014, Journal of Cryptographic Engineering.

MOLES: Malicious off-chip leakage enabled by side-channels

Christof Paar, Wayne P. Burleson, Lang Lin, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Prashant Jain, Dennis Goeckel, Russell Tessier, 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

Dynamically parameterized architectures for power-aware video coding: motion estimation and DCT

Prashant Jain, Wayne P. Burleson, Subramanian Venkatraman, 2001, Proceedings Second International Workshop on Digital and Computational Video.

Techniques for transient fault sensitivity analysis and reduction in VLSI circuits

Israel Koren, Wayne P. Burleson, Atul Maheshwari, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Modeling and analysis of Phase Change Materials for efficient thermal management

Houman Homayoun, Manish Arora, Dean M. Tullsen, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Reinforcement Learning for Thermal-aware Many-core Task Allocation

Russell Tessier, Wayne P. Burleson, Shiting Lu, 2015, ACM Great Lakes Symposium on VLSI.

Erasable PUFs: Formal Treatment and Generic Design

Marten van Dijk, Chenglu Jin, Ulrich Rührmair, 2020, ASHES@CCS.

Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering

Wayne P. Burleson, Jeongseon Euh, W. Burleson, 2000, PACS.

VLSI array algorithms and architectures for RSA modular multiplication

Wayne P. Burleson, Yongjin Jeong, W. Burleson, 1997, IEEE Trans. Very Large Scale Integr. Syst..

Efficient E-Cash in Practice: NFC-Based Payments for Public Transportation Systems

Christof Paar, Wayne P. Burleson, Anna Lysyanskaya, 2013, Privacy Enhancing Technologies.

Coding a terminated bus for low power

Mircea R. Stan, Wayne P. Burleson, W. Burleson, 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

A systolic VSLI chip for implementing orthogonal transforms

L. L. Scharf, W. P. Burleson, A. R. Gabriel, 1989 .

Digital systems design with ASIC and FPGA: a novel course using CD/DVD and on-line formats

Wayne P. Burleson, Sheng Xu, W. Burleson, 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).

On-chip lightweight implementation of reduced NIST randomness test suite

Wayne P. Burleson, Daniele Antonioli, Vikram B. Suresh, 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

A Dedicated Monitoring Infrastructure for Multicore Processors

Russell Tessier, Wayne P. Burleson, Jia Zhao, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A monitor interconnect and support subsystem for multicore processors

Russell Tessier, Wayne P. Burleson, Sailaja Madduri, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

Giovanni De Micheli, Wayne P. Burleson, Hu Xu, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

Jean-Luc Danger, Wayne P. Burleson, Andrés D. Garcia, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

Jean-Luc Danger, Wayne P. Burleson, Andrés David García García, 2000, FPGA '00.

A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS

Wayne P. Burleson, Basab Datta, W. Burleson, 2011, GLSVLSI '11.

Development of a Layout-Level Hardware Obfuscation Tool

Christof Paar, Wayne P. Burleson, Georg T. Becker, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Fine grained wearout sensing using metastability resolution time

Wayne P. Burleson, Vikram B. Suresh, Vikram B. Suresh, 2014, Fifteenth International Symposium on Quality Electronic Design.