R. Krishnamurthy

发表

High-Performance and Low-Voltage Sense-Amplifier Techniques for sub-90 nm SRAM

M. Sinha, S. Hsu, A. Alvandpour, 2003 .

A 2 GHz 13 . 6 mW 12 x 9 b Multiplier for Energy Efficient FFT Accelerators

S. Hsu, W. Burleson, R. Krishnamurthy, 2005 .

A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

S. Borkar, R.K. Krishnamurthy, S.K. Mathew, 2009, IEEE Journal of Solid-State Circuits.

An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations

C.H. Kim, S. Borkar, S. Hsu, 2004, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

Effectiveness and scaling trends of leakage control techniques for sub-130 nm CMOS technologies

S. Hsu, R. Krishnamurthy, S. Borkar, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2011, IEEE Journal of Solid-State Circuits.

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2009, IEEE Journal of Solid-State Circuits.

Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends

K. Soumyanath, R. Krishnamurthy, K. Mistry, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

S. Hsu, R. Krishnamurthy, V. Oklobdzija, 2005, IEEE Journal of Solid-State Circuits.

Current Comparison based Domino with Clamped Bit-Line Current Amplifier for Wide Fan-In Gates

A. Alvandpour, R. Krishnamurthy, A. Peiravi, 2016 .

Split-Path Fused Floating Point Multiply Accumulate (FPMAC)

Sanu Mathew, Ram Krishnamurthy, Tiju Jacob, 2013, 2013 IEEE 21st Symposium on Computer Arithmetic.

A low-leakage dynamic multi-ported register file in 0.13mm CMOS

Atila Alvandpour, Ram Krishnamurthy, Shekhar Y. Borkar, 2001, ISLPED '01.

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

K. Soumyanath, A. Alvandpour, R. Krishnamurthy, 2002, IEEE J. Solid State Circuits.

A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm CMOS

B. Bloechel, S. Borkar, S. Mathew, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends

K. Soumyanath, Sanu K. Mathew, Mark A. Anders, 2001 .

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2002 .

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2021, IEEE Journal of Solid-State Circuits.

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

B. Bloechel, S. Borkar, R.K. Krishnamurthy, 2004, IEEE Journal of Solid-State Circuits.

A 2.9–33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, 2019, IEEE Journal of Solid-State Circuits.

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations

Chaitali Chakrabarti, Gregory K. Chen, Ram Krishnamurthy, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Mixed Swing Techniques for Low Energy/Operation Datapath Circuits

Ram Kumar Krishnamurthy, R. Krishnamurthy, 1997 .

DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware

Gregory K. Chen, Phil V. Knag, R. Krishnamurthy, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs

Gregory K. Chen, Ram Krishnamurthy, Aravind Dasu, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Reconfigurable Computing: Architectures, Tools, and Applications

Tarek El-Ghazawi, Ram Krishnamurthy, John McAllister, 2014, Lecture Notes in Computer Science.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, IEEE Journal of Solid-State Circuits.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Himanshu Kaul, Amit Agarwal, Ram Krishnamurthy, 2012, IEEE Journal of Solid-State Circuits.

High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors

Ram Krishnamurthy, R. Krishnamurthy, 2010, ARC.

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2016, IEEE Journal of Solid-State Circuits.

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS

Gregory K. Chen, R. Krishnamurthy, Carlos Tokunaga, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

A 10-Output, Single-Inductor-Multiple-Output DC–DC Buck Converter With Integrated Output Capacitors for a Sub-mW System-on-Chip

Andrés A. Blanco, R. Krishnamurthy, Mingoo Seok, 2021, IEEE Solid-State Circuits Letters.

A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit

R.K. Krishnamurthy, S.K. Mathew, M.A. Anders, 2006, IEEE Journal of Solid-State Circuits.

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

S. Hsu, R. Krishnamurthy, J. Tschanz, 2022, European Solid-State Circuits Conference.

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 32nm 8.3GHz 64-entry × 32b variation tolerant near-threshold voltage register file

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators

Sanu Mathew, Mark Anders, Himanshu Kaul, 2019, 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH).

Staggered Metallization with Air gaps for Independently Tuned Interconnect Resistance and Capacitance

R. Krishnamurthy, M. Reshotko, H. Kaul, 2020, International Electron Devices Meeting.

A sub-130-nm conditional keeper technique

Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, 2002, IEEE J. Solid State Circuits.

Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era

Ram Krishnamurthy, Sriram Vangal, Vivek De, 2017, IEEE Design & Test.

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, IEEE Journal of Solid-State Circuits.

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

J. Tschanz, S. Narendra, R. Krishnamurthy, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

Reconfigurable Computing: Architectures, Tools, and Applications

R. Krishnamurthy, T. El-Ghazawi, A. Koch, 2014, Lecture Notes in Computer Science.