T. Shibata

发表

Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing

Tadashi Shibata, Tadahiro Ohmi, Tatsuo Morimoto, 1995, NIPS.

CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters

T. Shibata, T. Ohmi, K. Kotani, 1998, IEEE J. Solid State Circuits.

A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems

T. Shibata, Yitao Ma, 2009 .

Blind motion-blur parameter estimation using edge detectors

T. Shibata, Robert Grou-Szabo, 2009, 2009 3rd International Conference on Signal Processing and Communication Systems.

2 Low-Power Analog Associative Processors Employing Resonance-Type Current-Voltage Characteristics

T. Shibata, Trong-Tu Bui, 2018 .

Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors

Tadashi Shibata, T. Shibata, Trong-Tu Bui, 2008 .

Reverse‐bias current reduction in low‐temperature‐annealed silicon pn junctions by ultraclean ion‐implantation technology

T. Shibata, T. Ohmi, Y. Ishihara, 1990 .

Advanced scientific semiconductor processing based on high-precision controlled low-energy ion bombardment

Tadashi Shibata, Tadahiro Ohmi, T. Shibata, 1994 .

Study on further reducing the epitaxial silicon temperature down to 250 °C in low‐energy bias sputtering

T. Shibata, T. Ohmi, K. Hashimoto, 1991 .

Association hardware for intelligent electronic systems

Tadashi Shibata, Koji Kotani, Tadahiro Ohmi, 1999, Systems and Computers in Japan.

Special Issue on Vacuum Technology. Ultra Clean Technology for Semiconductor Manufacturing.

Tadashi Shibata, Tadahiro Ohmi, Tadashi Shibata, 1991 .

Design Optimization Of Gas Pumping System For Ultra Clean Reduced-Gas-Pressure Processing Equipment

T. Shibata, T. Ohmi, N. Konishi, 1994, International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM.

Neuron MOS voltage-mode circuit technology for multiple-valued logic

Tadahiro Ohmi, Tadashi Shibata, T. Shibata, 1993 .

Hardware Architecture for Pseudo-Two-Dimensional Hidden-Markov-Model-Based Face Recognition Systems Employing Laplace Distribution Functions

T. Shibata, Yasufumi Suzuki, 2007 .

Association hardware for intelligent electronic systems

Tadashi Shibata, Koji Kotani, Tadahiro Ohmi, 1999, Systems and Computers in Japan.

Low temperature, defect-free silicon epitaxy using a low kinetic energy particle process

T. Shibata, T. Ohmi, 1990 .

Very-low-temperature thin-film formation technology by a low-kinetic-energy particle process

T. Shibata, T. Ohmi, 1989 .

A low damage, low contaminant plasma processing system utilizing energy clean technology

Tadashi Shibata, Tadahiro Ohmi, Osamu Kamiya, 1991 .

Improvement of turbomolecular pumps for ultraclean, low-pressure, and high-gas-flow processing

T. Shibata, T. Ohmi, K. Sekine, 1998 .

Bio Inspired Architectures in the Nanoscale Integration Era

Tadashi Shibata, T. Shibata, 2009 .

Reducing Reverse-Bias Current in 450°C-Annealed n+p Junction by Hydrogen Radical Sintering

T. Shibata, T. Ohmi, A. Nakada, 1995 .

Coupled-Oscillator Associative Memory Array Operation

D. Hammerstrom, W. Porod, T. Shibata, 2013, 1304.6125.

Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits

T. Shibata, Renyuan Zhang, 2011 .

Patterning of human dental arch wire blanks using a vector quantization algorithm.

Tadashi Shibata, Kenji Takada, T. Shibata, 2002, The Angle orthodontist.

Room‐temperature copper metallization for ultralarge‐scale integrated circuits by a low kinetic‐energy particle process

Tadahiro Ohmi, Tatsuya Saito, T. Shibata, 1988 .

Formation of Copper Thin Films by a Low Kinetic Energy Particle Process

T. Shibata, T. Ohmi, M. Otsuki, 1991 .

Formation of device‐grade epitaxial silicon films at extremely low temperatures by low‐energy bias sputtering

Tadahiro Ohmi, T. Shibata, Hiroshi Iwabuchi, 1989 .

Evaluating the Large Electromigration Resistance of Copper Interconnects Employing a Newly Developed Accelerated Life‐Test Method

Tadashi Shibata, Tadahiro Ohmi, Takahisa Nitta, 1993 .

A gesture perception algorithm using compact one-dimensional representation of spatio-temporal motion-field patches

Tadashi Shibata, Ruihan Bao, T. Shibata, 2009, 2009 3rd International Conference on Signal Processing and Communication Systems.

A VLSI hardware implementation study of SVDD algorithm using analog Gaussian-cell array for on-chip learning

Renyuan Zhang, T. Shibata, T. Shibata, 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

A Directional-Edge-Based Face Detection Algorithm Adapted to the VLSI Image Recognition System

Tadashi Shibata, Yasufumi Suzuki, T. Shibata, 2011 .

Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition

Tadashi Shibata, Wolfgang Porod, Dmitri E. Nikonov, 2015, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

Electrical Properties of Giant‐Grain Copper Thin Films Formed by a Low Kinetic Energy Particle Process

Tadashi Shibata, Tadahiro Ohmi, Masahito Otsuki, 1992 .

Large-electromigration-resistance copper interconnect technology for sub-half-micron ULSI's

T. Shibata, T. Takewaki, T. Nitta, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)

Tadashi Shibata, Tadahiro Ohmi, Masahiro Konda, 1999 .

Electrical characterization of epitaxial silicon films formed by a low kinetic energy particle process

Tadashi Shibata, Tadahiro Ohmi, Hiroshi Iwabuchi, 1989 .

Formation of ultra-shallow low-reverse current n+p junctions by 450°C furnace annealing

T. Shibata, T. Ohmi, A. Okita, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

Formation of Copper Thin Films by a Low Kinetic Energy Particle Process.

T. Shibata, T. Ohmi, M. Otsuki, 1991 .

A single-chip 600-fps real-time action recognition system employing a hardware friendly algorithm

Nanning Zheng, Hongbo Zhu, Tadashi Shibata, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Non-Boolean associative architectures based on nano-oscillators

Yan Fang, T. Shibata, S. P. Levitan, 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

Evaluation of electromigration and stressmigration reliabilities of copper interconnects by a simple pulsed-current stressing technique

T. Shibata, T. Takewaki, H. Yamada, 1993, Proceedings of IEEE International Electron Devices Meeting.

Accelerated Electromigration Testing of Giant-Grain Copper Interconnects under Extremely Large Current Stress

T. Shibata, T. Ohmi, T. Takewaki, 1993 .

Influence of substrate‐boron concentration on the residual end‐of‐range defects in 450 °C annealed As+‐implanted junctions

T. Shibata, T. Ohmi, Y. Tamai, 1996 .

Depth Profile Of Point Defects In Ion Implanted n + p and p + n Junctions Formed By 450°C Post-Implantation Annealing And Impact Of Defects On Junction Characteristics

T. Shibata, T. Ohmi, Y. Tamai, 1996 .

An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine

Tadashi Shibata, Kyunghee Kang, T. Shibata, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Interested in publishing with us ? Contact book

T. Shibata, Yasufumi Suzuki, 2018 .

An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications

Tadashi Shibata, Yitao Ma, Tetsuo Endoh, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A functional MOS transistor featuring gate-level weighted sum and threshold operations

Tadashi Shibata, Tadahiro Ohmi, T. Shibata, 1992 .

Unsupervised Object Extraction by Contour Delineation and Texture Discrimination Based on Oriented Edge Features

Tadashi Shibata, Litian Sun, T. Shibata, 2014, IEEE Transactions on Circuits and Systems for Video Technology.

Ultra Clean Processing Technology

T. Shibata, T. Ohmi, 1991 .

Very-Low-Temperature Epitaxial Silicon Growth By Low-Kinetic-Energy Particle Bombardment

T. Shibata, T. Ohmi, T. Ichikawa, 1988 .

Eliminating Metal‐Sputter Contamination in Ion Implanter for Low‐Temperature‐Annealed, Low‐Reverse‐Bias‐Current Junctions

Tadashi Shibata, Tadahiro Ohmi, Takahisa Nitta, 1995 .

Thermal Stability Studies on Copper Thin Films Formed by a Low-Kinetic-Energy Particle Process

T. Shibata, T. Ohmi, M. Otsuki, 1989 .

Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements

M. Ogawa, Tadashi Shibata, Hitoshi Hayakawa, 2005 .

CMOS supporting circuitries for nano-oscillator-based associative memories

Renyuan Zhang, T. Shibata, S. P. Levitan, 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation

Hongbo Zhu, Pushe Zhao, Tadashi Shibata, 2013, IEEE Transactions on Circuits and Systems for Video Technology.

A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques

Tadashi Shibata, Trong Tu Bui, T. Shibata, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

Computing based on the physics of nano devices—A beyond-CMOS approach to human-like intelligent systems

Tadashi Shibata, T. Shibata, 2009 .

A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching

Tadashi Shibata, Yitao Ma, Tetsuo Endoh, 2011, 2011 International SoC Design Conference.

A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing

Tadashi Shibata, Kiyoto Ito, Benjamas Tongprasit, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A row-parallel cyclic-line-access edge detection CMOS image sensor employing global thresholding operation

Tadashi Shibata, Norihiro Takahashi, T. Shibata, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A neuron-MOS neural network using self-learning-compatible synapse circuits

Tadashi Shibata, Tadahiro Ohmi, Hiroshi Ishii, 1995, IEEE J. Solid State Circuits.

An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning Neuron-MOS neural networks

Tadashi Shibata, Tadahiro Ohmi, Hiroshi Ishii, 1993 .

Unsupervised object extraction by contour delineation and texture-based discrimination

Tadashi Shibata, Litian Sun, T. Shibata, 2012, 2012 Proceedings of the 20th European Signal Processing Conference (EUSIPCO).

A 600-μW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing Magnetic Tunnel Junction (MTJ) Based Nonvolatile Memories with Novel Intelligent Power-Gating (IPG) Scheme

Yitao Ma, Tetsuo Endoh, Takahiro Hanyu, 2015 .

A scalable architecture of associative processors employing nano functional devices

Tadashi Shibata, Trong Tu Bui, T. Shibata, 2009, 2009 10th International Conference on Ultimate Integration of Silicon.

A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter

Tadashi Shibata, Toshihiko Yamasaki, Tomoyuki Nakayama, 2009, Integr..

A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection

T. Yamasaki, T. Shibata, T. Shibata, 2007, IEEE Journal of Solid-State Circuits.

A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter

Tadashi Shibata, Toshihiko Yamasaki, Tomoyuki Nakayama, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A low-power and compact CDMA matched filter based on switched-current technology

T. Shibata, T. Yamasaki, T. Nakayama, 2005, IEEE Journal of Solid-State Circuits.

Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters

Tadashi Shibata, Toshihiko Yamasaki, Tomoyuki Nakayama, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation

Tadashi Shibata, Tadahiro Ohmi, T. Shibata, 1993 .