J. Craninckx

发表

A 79-GHz 2 $\times $ 2 MIMO PMCW Radar SoC in 28-nm CMOS

D. Guermandi, Q. Shi, A. Dewilde, 2017, IEEE Journal of Solid-State Circuits.

A 1 . 7 mW 11 b 250 MS / s 2 × Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

J. Craninckx, B. Verbruggen, M. Iriguchi, 2012 .

A CMOS 1.8 GHz low-phase-noise voltage-controlled oscillator with prescaler

M. Steyaert, J. Craninckx, Michel Steyaert, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

A fully integrated CMOS DCS-1800 frequency synthesizer

M. Steyaert, J. Craninckx, M. Steyaert, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A WLAN direct up-conversion mixer with automatic image rejection calibration

S. Donnay, J. Craninckx, B. Come, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Automatic calibration of a direct upconversion transmitter

J. Craninckx, S. Donnay, 2003, Radio and Wireless Conference, 2003. RAWCON '03. Proceedings.

Analysis and key specifications of a novel frequency synthesizer architecture for multi-standard transceivers

J. Craninckx, B. Come, J. Van Driessche, 2006, 2006 IEEE Radio and Wireless Symposium.

A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point

J. Borremans, J. Craninckx, V. Giannini, 2010, 2010 Proceedings of ESSCIRC.

Low-phase-noise gigahertz voltage-controlled oscillators in CMOS

J. Craninckx, M. Steyaert, 1995 .

1.1 GHz oscillator using bondwire inductance

M. Steyaert, J. Craninckx, 1994 .

A single-chip CMOS transceiver for DCS-1800 wireless communications

M. Steyaert, E. Morifuji, J. Craninckx, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A 21-dBm $I/Q$ Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology

Wagdy M. Gaber, M. Ingels, P. Wambacq, 2017, IEEE Transactions on Microwave Theory and Techniques.

Wideband VCO with Simultaneous Switching of Frequency Band, Active Core and Varactor Size

Jan Craninckx, B. Come, D. Hauspie, 2006 .

6 A 40 nm CMOS Highly Linear 0 . 4to-6 GHz Receiver Resilient to 0 dBm Out-of-Band Blockers

Jonathan Borremans, Jan Craninckx, Mark Ingels, 2011 .

A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

P. Wambacq, J. Borremans, J. Craninckx, 2017, International Congress on High-Speed Imaging and Photonics.

R 38 In-Pixel Storage Techniques for CMOS Burst-Mode Ultra-High-Speed Imagers

M. Rosmeulen, P. Wambacq, J. Craninckx, 2017 .

A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS

André Bourdoux, Jan Craninckx, Davide Guermandi, 2017, IEEE J. Solid State Circuits.

Phase Modulated MM-Wave Radars in Advanced CMOS Technology

D. Guermandi, A. Bourdoux, P. Wambacq, 2018, 2018 Asia-Pacific Microwave Conference (APMC).

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers

Jan Craninckx, Piet Wambacq, Ewout Martens, 2019, IEEE J. Solid State Circuits.

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a

Jan Craninckx, Geert Van der Plas, Julien Ryckaert, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A Design Approach for Power-Optimized Fully Reconfigurable $\Delta \Sigma$ A/D Converter for 4G Radios

Georges G. E. Gielen, Jan Craninckx, Yi Ke, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS

Jan Craninckx, Badr Malki, Bob Verbruggen, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers

Jonathan Borremans, Jan Craninckx, Mark Ingels, 2011, 2011 IEEE International Solid-State Circuits Conference.

SAW-less software-defined radio transceivers in 40nm CMOS

Jonathan Borremans, Jan Craninckx, Mark Ingels, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A 1.8-GHz low-phase-noise spiral-LC CMOS VCO

M. Steyaert, J. Craninckx, J. Craninckx, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

A Wideband 62-mW 60-GHz FMCW Radar in 28-nm CMOS

P. Wambacq, J. Craninckx, Anirudh Kankuppe, 2021, IEEE Transactions on Microwave Theory and Techniques.

An area efficient digital amplitude modulator in 90nm CMOS

Andrea Baschirotto, Jan Craninckx, Vincenzo Chironi, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

Jan Craninckx, Piet Wambacq, Kuba Raczkowski, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation

P. Wambacq, J. Craninckx, N. Markulić, 2019, Analog Circuits and Signal Processing.

A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter

J. Craninckx, B. Hershberg, J. Van Driessche, 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.

A 100KHz – 20MHz source follower continuous time filter for SDR applications

P. Wambacq, J. Craninckx, A. Baschirotto, 2017 .

Part I Transceiver Concepts and Design

J. Craninckx, 2010 .

A 2.4 GHz Low-Power Sixth-Order RF Bandpass

J. Ryckaert, J. Craninckx, B. Verbruggen, 2009 .

F3: Radio architectures and circuits towards 5G

Kenichi Okada, Ahmad Mirzaei, Stefano Pellerano, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Design and Characterization of a 3 . 5 um pitch , 8192 resolution , 5 Spectrum CMOS TDI image sensor

M. Rosmeulen, J. Craninckx, L. Haspeslagh, 2017 .

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS

J. Craninckx, G. V. D. Plas, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL.

Michiel Steyaert, Kameswaran Vengattaramane, Jan Craninckx, 2009, ISCAS 2009.

Multiplexed superconducting qubit control at millikelvin temperatures with a low-power cryo-CMOS multiplexer

Georges G. E. Gielen, B. Govoreanu, I. Radu, 2022, Nature Electronics.

Apparatus and method for generating a signal with a predefined when starting transients

Jan Craninckx, Julien Ryckaert, J. Ryckaert, 2007 .

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Jan Craninckx, Ewout Martens, Nick Van Helleputte, 2019, IEEE Transactions on Biomedical Circuits and Systems.

Millikelvin temperature cryo-CMOS multiplexer for scalable quantum device characterisation

T. Ivanov, B. Govoreanu, I. Radu, 2020, Quantum Science and Technology.

4G terminals: how are we going to design them?

Jan Craninckx, Stéphane Donnay, J. Craninckx, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Analog/RF Solutions Enabling Compact Full-Duplex Radios

Eric A. M. Klumperink, Bram Nauta, Jan Craninckx, 2014, IEEE Journal on Selected Areas in Communications.

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation

Yves Rolain, Gerd Vandersteen, Pierluigi Nuzzo, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration

Michiel Steyaert, Jonathan Borremans, Kameswaran Vengattaramane, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Transactions on Microwave Theory and Techniques.

Calibration of Direct-Conversion Transceivers

Gerd Vandersteen, Jan Craninckx, Björn Debaillie, 2009, IEEE Journal of Selected Topics in Signal Processing.

Impact of front-end effects on the performance of downlink OFDM-MIMO transmission

P. Wambacq, A. Barel, S. Donnay, 2004, Proceedings. 2004 IEEE Radio and Wireless Conference (IEEE Cat. No.04TH8746).

Power Efficient Reconfigurable Baseband Filters for Multimode Radios

Michiel Steyaert, Jan Craninckx, Pieter Crombez, 2009 .

A 100kHz – 20MHz reconfigurable nauta gm-C biquad low-pass filter in 0.13µm CMOS

M. Steyaert, J. Craninckx, P. Crombez, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A linearity and power efficient design strategy for architecture optimization of gm-C biquadratic filters

M. Steyaert, J. Craninckx, P. Crombez, 2007, 2007 Ph.D Research in Microelectronics and Electronics Conference.

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

Andrea Baschirotto, Jan Craninckx, Stefano D'Amico, 2007, IEEE Journal of Solid-State Circuits.

A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

Andrea Baschirotto, Liesbet Van der Perre, T. Kim, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS

Michiel Steyaert, Pierluigi Nuzzo, Kameswaran Vengattaramane, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 48-dB DR 80-MHz BW 8.88-GS/s bandpass ΔΣ ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

Jan Craninckx, Andre Bourdoux, Julien Ryckaert, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

High speed CMOS analog interface circuits for single chip telecommunication systems

Michel Steyaert, Stefan Gogaert, Jan Craninckx, 1996 .

Low phase-noise VCO circuits: from external components to full CMOS integration

Michel Steyaert, Jan Craninckx, M. Steyaert, 1997 .

RF self-interference cancellation for full-duplex

Eric A. M. Klumperink, Jan Craninckx, Björn Debaillie, 2014, 2014 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CROWNCOM).

Analog CMOS interface circuits for single-chip digital telecommunication systems: the challenge of the future

Michel Steyaert, Stefan Gogaert, Jan Craninckx, 1995 .

Green Reconfigurable Radio Systems

André Bourdoux, Liesbet Van der Perre, Bruno Bougard, 2007, IEEE Signal Processing Magazine.

A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS

P. Wambacq, J. Craninckx, Dae-Woong Park, 2022, IEEE Journal of Solid-State Circuits.

A 135-155 GHz 9.7%/16.6% DC-RF/DC-EIRP Efficiency Frequency Multiply-by-9 FMCW Transmitter in 28 nm CMOS

P. Wambacq, J. Craninckx, Dae-Woong Park, 2021, Radio Frequency Integrated Circuits Symposium.

A 2.8-to-8.5mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CTΔΣ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS

Peng Gao, Georges Gielen, Jan Craninckx, 2010, 2010 Symposium on VLSI Circuits.

A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS

Michiel Steyaert, Jan Craninckx, Geert Van der Plas, 2010, IEEE Journal of Solid-State Circuits.

Low-noise voltage-controlled oscillators using enhanced LC-tanks

Michiel Steyaert, Jan Craninckx, J. Craninckx, 1995 .

Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

Eun-Chul Park, J. Craninckx, D. Hauspie, 2007, IEEE Journal of Solid-State Circuits.

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

P. Wambacq, J. Craninckx, B. Hershberg, 2022, IEEE Journal of Solid-State Circuits.

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

Michiel Steyaert, Jan Craninckx, J. Craninckx, 1997, IEEE J. Solid State Circuits.

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Andrea Baschirotto, Pierluigi Nuzzo, Jan Craninckx, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

Jan Craninckx, Takaya Yamamoto, Ewout Martens, 2015, IEEE Journal of Solid-State Circuits.

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass $\Delta\Sigma$ Modulator and Polyphase Decimation Filter

André Bourdoux, Jan Craninckx, Geert Van der Plas, 2012, IEEE Journal of Solid-State Circuits.

Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper)

Steven Brebels, Jan Craninckx, Andre Bourdoux, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Adaptive RF Front-Ends Using Electrical-Balance Duplexers and Tuned SAW Resonators

Jan Craninckx, Piet Wambacq, Akshay Visweswaran, 2017, IEEE Transactions on Microwave Theory and Techniques.

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Journal of Solid-State Circuits.

A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems

Michiel Steyaert, Jan Craninckx, H. Miyakawa, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

Jan Craninckx, Benjamin P. Hershberg, Kuba Raczkowski, 2015, IEEE Journal of Solid-State Circuits.

Design and Analysis of 55–63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS

P. Wambacq, J. Craninckx, G. Mangraviti, 2022, IEEE Journal of Solid-State Circuits.

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

Jan Craninckx, Piet Wambacq, Cheng-Hsueh Tsai, 2020, IEEE Journal of Solid-State Circuits.

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

P. Wambacq, A. Bevilacqua, J. Borremans, 2008, IEEE Journal of Solid-State Circuits.

Flicker noise upconversion mechanisms in K-band CMOS VCOs

Jan Craninckx, Davide Guermandi, Piet Wambacq, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter

Jan Craninckx, Piet Wambacq, Mark Ingels, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2019, IEEE Journal of Solid-State Circuits.

A 2×14bit digital transmitter with memoryless current unit cells and integrated AM/PM calibration

Yao Liu, Jan Craninckx, Mark Ingels, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

An Incremental-Charge-Based Digital Transmitter With Built-in Filtering

Jan Craninckx, Piet Wambacq, Mark Ingels, 2015, IEEE Journal of Solid-State Circuits.

13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with −159dBc/Hz out-of-band noise

Jan Craninckx, Piet Wambacq, Mark Ingels, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

Jan Craninckx, Geert Van der Plas, Julien Ryckaert, 2007, IEEE Journal of Solid-State Circuits.

Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

P. Wambacq, J. Craninckx, N. Markulić, 2019, Analog Circuits and Signal Processing.

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2020, IEEE Journal of Solid-State Circuits.

A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA

Pui-In Mak, Jan Craninckx, Rui P. Martins, 2018, IEEE Journal of Solid-State Circuits.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

Jonathan Borremans, Jan Craninckx, Björn Debaillie, 2011, IEEE Journal of Solid-State Circuits.

16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation

Rui P. Martins, Chi-Hang Chan, Jan Craninckx, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 6.5-kV ESD-protected 3-5-GHz ultra-wideband BiCMOS low-noise amplifier using interstage gain roll-off compensation

M. Kuijk, N.M. Iyer, J. Craninckx, 2005, IEEE Transactions on Microwave Theory and Techniques.

In-band full-duplex transceiver technology for 5G mobile networks

Eric A. M. Klumperink, Bram Nauta, Jan Craninckx, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

An in-band full-duplex transceiver prototype with an in-system automated tuning for RF self-interference cancellation

Jan Craninckx, Barend van Liempd, Bjorn Debaillie, 2014, 1st International Conference on 5G for Ubiquitous Connectivity.

Wireless CMOS Frequency Synthesizer Design

Michiel Steyaert, Jan Craninckx, J. Craninckx, 1998 .

A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS

Alberto L. Sangiovanni-Vincentelli, Pierluigi Nuzzo, Jan Craninckx, 2009, 2009 Symposium on VLSI Circuits.

A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μM CMOS

Michiel Steyaert, Jan Craninckx, J. Craninckx, 1996, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler

Michiel Steyaert, Jan Craninckx, M. Steyaert, 1995, IEEE J. Solid State Circuits.

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS

J. Ryckaert, P. Wambacq, J. Craninckx, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz

M. Steyaert, P. Kinget, J. Craninckx, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

A Single Bit 6.8mW 10MHz Power-Optimized CTDS with 67dB DR in 90nm CMOS

Michel Steyaert, Jan Craninckx, Geert Van der Plas, 2009 .

A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer

J. Craninckx, M.S.J. Steyaert, W. Laflere, 2008, IEEE Journal of Solid-State Circuits.

A power amplifier driver using self-oscillating pulse-width modulators

Michiel Steyaert, Jan Craninckx, Willem Laflere, 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

Switched RF Transmitters

J. Craninckx, M. Steyaert, W. Laflere, 2008 .

A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout

Steven Brebels, Jan Craninckx, Piet Wambacq, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).