Hiran Tennakoon

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

Hiran Tennakoon, C. Sechen, 2002, ICCAD 2002.

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

Hiran Tennakoon, Carl Sechen, Hiran Tennakoon, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Nonconvex Gate Delay Modeling and Delay Optimization

Hiran Tennakoon, Carl Sechen, Hiran Tennakoon, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Power reduction via near-optimal library-based cell-size selection

Hiran Tennakoon, Carl Sechen, Mohammad Rahman, 2011, 2011 Design, Automation & Test in Europe.

Efficient and accurate gate sizing with piecewise convex delay models

Hiran Tennakoon, C. Sechen, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Power reduction via separate synthesis and physical libraries

Hiran Tennakoon, Carl Sechen, Mohammad Rahman, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).