C. Liu

发表

Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs

M. H. Lee, K. Chen, C.-Y. Liao, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Mobility Calculation of Ge Nanowire Junctionless and Inversion-Mode Nanowire NFETs With Size and Shape Dependence

C. Liu, Hung-Yu Ye, Chia-Che Chung, 2018, IEEE Transactions on Electron Devices.

C. Liu, C. Chou, Chia-Chun Yen, 2020, IEEE Journal of the Electron Devices Society.

Enhanced Current Drive of Double-Gate $\alpha$ -IGZO Thin-Film Transistors

C. W. Liu, C. Liu, C. Chou, 2013, IEEE Electron Device Letters.

Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs

C. Liu, W. K. Wan, Hung-Yu Ye, 2019, IEEE Electron Device Letters.

Thermal SPICE Modeling of FinFET and BEOL Considering Frequency-Dependent Transient Response, 3-D Heat Flow, Boundary/Alloy Scattering, and Interfacial Thermal Resistance

C. Liu, W. K. Wan, Chia-Che Chung, 2019, IEEE Transactions on Electron Devices.

First vertically stacked GeSn nanowire pGAAFETs with Ion = 1850μA/μm (Vov = Vds = −1V) on Si by GeSn/Ge CVD epitaxial growth and optimum selective etching

C. Liu, Chih-hao Huang, Chung-yi Lin, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Effects of Annealing Temperature and Nitrogen Content on Effective Work Function of Tungsten Nitride

C. Liu, Chih-Hsiung Huang, Chung-En Tsai, 2019, IEEE Electron Device Letters.

Improved Ferroelectricity in Cryogenic Phase Transition of Hf0.5Zr0.5O2

C. Liu, Yun-Wen Chen, Yifan Xing, 2022, IEEE Journal of the Electron Devices Society.

ION Enhancement of Ge0.98Si0.02 Nanowire nFETs by High-κ Dielectrics

C. Liu, Yifan Xing, Yu-Rui Chen, 2022, IEEE Electron Device Letters.

Low Contact Resistivity to Ge Using In-Situ B and Sn Incorporation by Chemical Vapor Deposition

C. Liu, Hung-Yu Ye, Fang-Liang Lu, 2020, IEEE Transactions on Electron Devices.

First Highly Stacked Ge0.95Si0.05 nGAAFETs with Record ION = 110 μA (4100 μA/μm) at VOV=VDS=0.5V and High Gm,max = 340 μS (13000 μS/μm) at VDS=0.5V by Wet Etching

C. Liu, Sun-Rong Jan, Chung-En Tsai, 2021, Symposium on VLSI Technology.

First Vertically Stacked Tensily Strained Ge0.98Si0.02 nGAAFETs with No Parasitic Channel and LG = 40 nm Featuring Record ION = 48 μA at VOV=VDS=0.5V and Record Gm,max(μS/μm)/SSSAT(mV/dec) = 8.3 at VDS=0.5V

C. Liu, Chung-yi Lin, Fang-Liang Lu, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch

C. Liu, Hung-Yu Ye, Fang-Liang Lu, 2021, IEEE Transactions on Electron Devices.

Optical Detection of Parasitic Channels of Vertically Stacked Ge0.98Si0.02 nGAAFETs

C. Liu, Fang-Liang Lu, Yu-Shiang Huang, 2020, IEEE Transactions on Electron Devices.

On-Current Enhancement in TreeFET by Combining Vertically Stacked Nanosheets and Interbridges

C. Liu, Hung-Yu Ye, 2020, IEEE Electron Device Letters.

RF Performance of Stacked Si Nanosheets/Nanowires

C. Liu, Chia-Che Chung, Sun-Rong Jan, 2022, IEEE Electron Device Letters.

Dopant Recovery in Epitaxial Ge on SOI by Laser Annealing With Device Applications

C. Liu, I-Hsieh Wong, Fang-Liang Lu, 2018, IEEE Transactions on Electron Devices.

Ferroelectric Al:HfO2 negative capacitance FETs

M. H. Lee, C.-Y. Liao, S. Gu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs

M. H. Lee, C.-H. Tang, M.-H. Liao, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Negative capacitance FETs with steep switching by ferroelectric Hf-based oxide

M. H. Lee, C.-Y. Kuo, C. W. Liu, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Vertically Stacked Strained 3-GeSn-Nanosheet pGAAFETs on Si Using GeSn/Ge CVD Epitaxial Growth and the Optimum Selective Channel Release Process

C. Liu, Hung-Yu Ye, Fang-Liang Lu, 2018, IEEE Electron Device Letters.

Mobility Enhancement of Back-Channel-Etch Amorphous InGaZnO TFT by Double Layers With Quantum Well Structures

C. Liu, C. Chou, Chia-Chun Yen, 2019, IEEE Transactions on Electron Devices.

Fatigue Mechanism of Antiferroelectric Hf0.1Zr0.9O2 Toward Endurance Immunity by Opposite Polarity Cycling Recovery (OPCR) for eDRAM

M. H. Lee, Y. Chen, C. Liu, 2023, IEEE Transactions on Electron Devices.

Performance Improvement by Double-Layer a-IGZO TFTs With a Top Barrier

C. Liu, C. Chou, Chia-Chun Yen, 2022, IEEE Journal of the Electron Devices Society.

Mobility Enhancement and Abnormal Humps in Top-Gate Self-Aligned Double-Layer Amorphous InGaZnO TFTs

C. Liu, C. Chou, Chia-Chun Yen, 2022, IEEE Journal of the Electron Devices Society.

RF Performance Optimization of Stacked Si Nanosheet nFETs

C. Liu, Chia-Che Chung, Chia-Jung Tsen, 2022, International Symposium on VLSI Technology, Systems, and Applications.

First Demonstration of Interface-Enhanced SAF Enabling 400°C-Robust 42 nm p-SOT-MTJ Cells with STT-Assisted Field-Free Switching and Composite Channels

C. Liu, Cho-Lun Hsu, D. Tang, 2021, 2021 Symposium on VLSI Technology.

Critical Current Reduction of Field-Free Perpendicular SOT-MTJ by STT Assist Using Micromagnetic Simulation

C. Liu, Wei‐Jen Chen, Ya-Jui Tsou, 2021, International Conference on Simulation of Semiconductor Processes and Devices.

Experimental Demonstration of TreeFETs Combining Stacked Nanosheets and Low Doping Interbridges by Epitaxy and Wet Etching

C. Liu, Chung-En Tsai, Yu-Rui Chen, 2022, IEEE Electron Device Letters.

Self-Heating Mitigation of TreeFETs by Interbridges

C. Liu, Chia-Che Chung, Chia-Jung Tsen, 2022, IEEE Transactions on Electron Devices.

Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry

C. Liu, W. K. Wan, Chia-Che Chung, 2020, 2020 IEEE Symposium on VLSI Technology.

Novel vertically stacked Ge0.85Si0.15 nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhanced Ion (1.7X at VOV = VDS = 0.5 V) by Ge0.85Si0.15 channels

C. Liu, Hung-Yu Ye, Fang-Liang Lu, 2020, Semiconductor Science and Technology.

Highly Stacked GeSn Nanosheets by CVD Epitaxy and Highly Selective Isotropic Dry Etching

C. Liu, Sun-Rong Jan, Chung-En Tsai, 2022, IEEE Transactions on Electron Devices.

First Demonstration of Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets with Record ION =73μA at VOV=VDS= -0.5V and Low Noise Using Double Ge0.95Sn0.05 Caps, Dry Etch, Low Channel Doping, and High S/D Doping

C. Liu, Hung-Yu Ye, Fang-Liang Lu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

RF Performance of Stacked Si Nanosheet nFETs

C. Liu, Chia-Che Chung, B. Huang, 2021, IEEE Transactions on Electron Devices.

Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects

C. Liu, W. K. Wan, Y.-H. Huang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Strain effect on the stability in ferroelectric HfO2 simulated by first-principles calculations

C. Liu, Yun-Wen Chen, Sheng-Ting Fan, 2020, Journal of Physics D: Applied Physics.

Record high mobility (428cm2/V-s) of CVD-grown Ge/strained Ge0.91Sn0.09/Ge quantum well p-MOSFETs

C. Liu, Chih-Hsiung Huang, Chung-yi Lin, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).