P. Sung

发表

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Chia-Chen Wan, C. Wang, C. Su, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction

Yao-Jen Lee, T. Hou, F. Hou, 2016, IEEE Transactions on Electron Devices.

High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications

Yao-Jen Lee, F. Hou, P. Sung, 2017, IEEE Transactions on Electron Devices.

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Yao-Jen Lee, C. Su, P. Sung, 2020, IEEE Transactions on Electron Devices.

Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal

Yao-Jen Lee, P. Sung, T. Chao, 2014 .

Random Variation in Nanoscale HfZrO$_2$ Ferroelectric FinFETs: Physical Origin and Neuromorphic System Implications

Yao-Jen Lee, C. Su, P. Sung, 2020 .

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

Yao-Jen Lee, C. Hu, P. Sung, 2012, 2012 International Electron Devices Meeting.

Well-behaved Ge n+/p shallow junction achieved by plasma immersion ion implantation

P. Sung, B. Tsui, Yi-Ju Chen, 2020 .

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Yao-Jen Lee, C. Hu, P. Sung, 2014, IEEE Transactions on Electron Devices.

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

C. Su, P. Sung, D. Lu, 2022, Frontiers in Nanotechnology.

Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology

Yao-Jen Lee, P. Sung, W. Yeh, 2021, 2021 Symposium on VLSI Technology.

Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K

Sourav De, Yao-Jen Lee, Chun-Jung Su, 2020, 2020 Device Research Conference (DRC).

Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering

Yao-Jen Lee, C. Su, P. Sung, 2021 .

Study on the Roles of Charge Trapping and Fixed Charge on Subthreshold Characteristics of FeFETs

C. Su, P. Sung, C. Jin, 2021, IEEE Transactions on Electron Devices.

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

G. Huang, Yao-Jen Lee, F. Hou, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices

P. Sung, K. Kao, T. Tseng, 2017 .

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

W.-F. Wu, C. Wang, C. Su, 2017, 2017 Symposium on VLSI Technology.

3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

C. Yao, C. Su, T. Hong, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment

C. J. Wang, C. Su, T. Hong, 2018, IEEE Journal of the Electron Devices Society.

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Yao-Jen Lee, C. Su, P. Sung, 2020, IEEE Journal of the Electron Devices Society.

Nearly defect-free Ge gate-all-around FETs on Si substrates

C. Hu, P. Sung, G. Luo, 2011, 2011 International Electron Devices Meeting.

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

P. Sung, K. Kao, Y. Lee, 2014, 2014 IEEE International Electron Devices Meeting.

Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

Sourav De, Bo-Han Qiu, Md. Aftab Baig, 2021, IEEE Electron Device Letters.

Suspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETs

Tuo-Hung Hou, Seiji Samukawa, Fu-Kuo Hsueh, 2016, IEEE Transactions on Electron Devices.

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Guo-Wei Huang, Tuo-Hung Hou, Tien-Sheng Chao, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels

G. Huang, C. Hu, F. Hou, 2012, 2012 International Electron Devices Meeting.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

J. Tarng, Kun-Ming Chen, G. Huang, 2022, IEEE Transactions on Electron Devices.

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

C. Wang, C. Su, P. Sung, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

H. J. Chen, J. Tarng, C. Su, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks

Yao-Jen Lee, P. Sung, C. Luo, 2013, IEEE Electron Device Letters.

3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

C. Su, P. Sung, Wen-Hsi Lee, 2023, IEEE Journal of the Electron Devices Society.

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

T. Hong, P. Sung, K. Kao, 2022, 2022 International Electron Devices Meeting (IEDM).

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

P. Sung, G. Luo, W. Yeh, 2022, 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Random Variations in Hf$_{0.5}$Zr$_{0.5}$O$_2$ based FE-finFETs: A Synergistic Approach of Interfacial Layer Engineering and Mixed Precision Architecture to Mitigate the Implications on Deep Neural Networks.

Yao-Jen Lee, P. Sung, D. Lu, 2020 .

Low temperature microwave annealed FinFETs with less Vth variability

P. Sung, Y. Lee, K. Endo, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Low-temperature microwave annealing processes for future IC fabrication

Yao-Jen Lee, P. Sung, T. Chao, 2014, 2014 IEEE International Nanoelectronics Conference (INEC).