G. Luo

发表

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Chia-Chen Wan, C. Wang, C. Su, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio

G. Luo, Yung-Chun Wu, Chong-Jhe Sun, 2020, IEEE Journal of the Electron Devices Society.

Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors

Chun-Yen Chang, Xiao Gong, Yee-Chia Yeo, 2011 .

A new self-aligned contact technology for III-V MOSFETs

Chun-Yen Chang, Y. Yeo, G. Luo, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Thermally induced morphology evolution of pit-patterned Si substrate and its effect on nucleation properties of Ge dots

G. Luo, C. Kuan, Fu-Min Wang, 2012, Nanotechnology.

Ge GAA FETs and TMD FinFETs for the Applications Beyond Si—A Review

Jia-Min Shieh, Chih-Chao Yang, Chang-Hong Shen, 2016, IEEE Journal of the Electron Devices Society.

High-Performance and Low-Temperature-Compatible p-Channel Polycrystalline-Silicon TFTs Using

G. Luo, Tiao-Yuan Huang, Ming-Jui Yang, 2007 .

High-Mobility GeSn n-Channel MOSFETs by Low-Temperature Chemical Vapor Deposition and Microwave Annealing

G. Luo, C. Shen, Y. Chuang, 2018, IEEE Electron Device Letters.

High Dopant Activation of Phosphorus in Strained and Relaxed GeSn by Rapid Thermal Annealing and Microwave Annealing

G. Luo, Y. Chuang, Chia-You Liu, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Thermochemical reaction of ZrOx(Ny) interfaces on Ge and Si substrates

Chun-Yen Chang, G. Luo, C. Chien, 2006 .

Phase-separation phenomenon of NiGePt alloy on n-Ge by microwave annealing

G. Luo, C. Chien, Kun‐Lin Lin, 2018 .

Optical characterization of ZnSe epilayers and ZnCdSe∕ZnSe quantum wells grown on Ge∕Ge0.95Si0.05∕Ge0.9Si0.1∕Si virtual substrates

G. Luo, C. Y. Chang, D. Chuu, 2006 .

Fabricating a n+-Ge contact with ultralow specific contact resistivity by introducing a PtGe alloy as a contact metal

G. Luo, C. Chien, Cheng-Wei Chou, 2015 .

Study of the Erase Mechanism of MANOS ($ \hbox{Metal/Al}_{2}\hbox{O}_{3}/\hbox{SiN/SiO}_{2}/\hbox{Si}$) Device

E. Lai, K. Hsieh, Chih-Yuan Lu, 2007, IEEE Electron Device Letters.

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

Yao-Jen Lee, C. Hu, P. Sung, 2012, 2012 International Electron Devices Meeting.

Growth behaviour of Ge nano-islands on the nanosized Si{111} facets bordering on two {100} planes

G. Luo, M. Hsieh, Kai-Ming Yang, 2006 .

Fully depleted GeOI-channel junctionless pMOSFET with a low-resistance-raised NiGe alloy S/D

G. Luo, C. Chien, Wei-Li Lee, 2017 .

High On/Off Ratio and Very Low Leakage in p+/n and n+/p Germanium/Silicon Heterojunction Diodes

G. Luo, C. Chien, C. Chung, 2013 .

Effects of Minority-Carrier Response Behavior on Ge MOS Capacitor Characteristics: Experimental Measurements and Theoretical Simulations

Chun-Yen Chang, G. Luo, C. Chien, 2009, IEEE Transactions on Electron Devices.

Characteristics of Atomic-Layer-Deposited Al2O3 High-k Dielectric Films Grown on Ge Substrates

Chun-Yen Chang, G. Luo, C. Chien, 2008 .

Improved Electrical Properties of Gd2O3 ∕ GaAs Capacitor with Modified Wet-Chemical Clean and Sulfidization Procedures

Chun-Yen Chang, G. Luo, C. Chien, 2008 .

Optimization of the growth of the InGaP etch-stop layer by MOVPE for InGaP/GaAs HBT device application

G. Luo, C. Y. Chang, E. Chang, 2006 .

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

Chun-Yen Chang, G. Luo, E. Chang, 2005 .

Use of Si+ pre-ion-implantation on Si substrate to enhance the strain relaxation of the GexSi1-x metamorphic buffer layer for the growth of Ge layer on Si substrate

Chun-Yen Chang, G. Luo, M. Pilkuhn, 2007 .

Self-assembled In0.22Ga0.78As quantum dots grown on metamorphic GaAs∕Ge∕SixGe1−x∕Si substrate

G. Luo, C. Y. Chang, Shyh Wang, 2006 .

Self-assembled In/sub 0.22/Ga/sub 0.78/As quantum dots grown on GaAs/Ge/Si/sub x/Ge/sub 1-x//Si substrate

G. Luo, E. Chang, D. Biswas, 2005, 5th IEEE Conference on Nanotechnology, 2005..

Flower-Like Distributed Self-Organized Ge Dots on Patterned Si (001) Substrates

G. Luo, E. Chang, H. Lee, 2003 .

High-speed GaAs metal gate semiconductor field effect transistor structure grown on a composite Ge/GexSi1-x/Si substrate

Chun-Yen Chang, G. Luo, C. Chien, 2007 .

Study of Nickel Silicide Contact on

Chun-Yen Chang, G. Luo, E. Chang, 2003 .

The Annihilation of Threading Dislocations in the Germanium Epitaxially Grown within the Silicon Nanoscale Trenches

Chun-Yen Chang, G. Luo, C. Wann, 2009 .

Aggressive Equivalent Oxide Thickness of ~0.7 nm on Si0.8Ge0.2 Through HfO2 Dielectric Direct Deposition

G. Luo, C. Chien, Shin-Yuan Wang, 2022, IEEE Electron Device Letters.

SiGe and Si Gate-All-Around FET Fabricated by Selective Etching the Same Epitaxial Layers

G. Luo, C. Chu, Chun-Hsiung Lin, 2022, 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).

Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs

Chun-Yen Chang, G. Luo, C. Wann, 2010 .

Thermal conductivity of Si/SiGe superlattice films

G. Luo, Shih-Chiang Huang, M. Dai, 2008 .

Competitiveness between direct and indirect radiative transitions of Ge

T.-H. Cheng, Chih-Wen Liu, C.-Y. Ko, 2010 .

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

W.-F. Wu, C. Wang, C. Su, 2017, 2017 Symposium on VLSI Technology.

Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications

G. Luo, C. Chu, Szu-Hung Chen, 2023, Scientific reports.

Stacked Ge-Nanosheet GAAFETs Fabricated by Ge/Si Multilayer Epitaxy

G. Luo, W. Yeh, C. Chu, 2018, IEEE Electron Device Letters.

Demonstration of HfO2-Based Gate Dielectric With ~0.8-nm Equivalent Oxide Thickness on Si0.8Ge0.2 by Trimethylaluminum Pre-Treatment and Al Scavenger

G. Luo, C. Chien, Shin-Yuan Wang, 2023, IEEE Journal of the Electron Devices Society.

Effect of surface Si redistribution on the alignment of Ge dots grown on pit-patterned Si(001) substrates

G. Luo, C. Kuan, Sao-Jie Chen, 2014, Nanotechnology.

Photoluminescence investigation of strictly ordered Ge dots grown on pit-patterned Si substrates

G. Luo, C. Kuan, Sao-Jie Chen, 2014 .

High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response

C. Hu, G. Luo, Fu-Liang Yang, 2010, 2010 International Electron Devices Meeting.

Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment

C. J. Wang, C. Su, T. Hong, 2018, IEEE Journal of the Electron Devices Society.

A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices

Rich Liu, Kuang-Yeu Hsieh, Chih-Yuan Lu, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Growth and characterization of Ge nanostructures selectively grown on patterned Si

G. Luo, M. Cheng, W. Ni, 2008 .

Study of thermal stability of HfOxNy/Ge capacitors using postdeposition annealing and NH3 plasma pretreatment

Chun-Yen Chang, Chao-Hsin Chien, Chih-Kuo Tseng, 2007 .

Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High ${\rm I}_{\rm ON}/{\rm I}_{\rm OFF}$ Ratio Ge FinFETs

G. Luo, C. Chien, C. Kei, 2013, IEEE Transactions on Electron Devices.

Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel

G. Luo, C. Chien, C. Chung, 2014, IEEE Electron Device Letters.

Nearly defect-free Ge gate-all-around FETs on Si substrates

C. Hu, P. Sung, G. Luo, 2011, 2011 International Electron Devices Meeting.

Effects of interfacial sulfidization and thermal annealing on the electrical properties of an atomic-layer-deposited Al2O3 gate dielectric on GaAs substrate

Chun-Yen Chang, G. Luo, C. Chien, 2008 .

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

Bo-Yuan Chen, Jiann-Lin Chen, Edward Yi Chang, 2017 .

Microwave Annealing for NiSiGe Schottky Junction on SiGe P-Channel

G. Luo, C. Chien, Yi-He Tsai, 2015, Materials.

Germanium N and P Multifin Field-Effect Transistors With High-Performance Germanium (Ge) ${\rm p}^{+}/{\rm n}$ and ${\rm n}^{+}/{\rm p}$ Heterojunctions Formed on Si Substrate

Chao-Hsin Chien, G. Luo, C. Chien, 2013, IEEE Transactions on Electron Devices.

C-V characteristics of epitaxial germanium metal-oxide-semiconductor capacitor on GaAs substrate with ALD Al2O3 dielectric

G. Luo, M. Hudait, E. Chang, 2012 .

Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD- $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric

Chun-Yen Chang, G. Luo, C. Chien, 2009, IEEE Transactions on Electron Devices.

Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al 2 O 3

Chun-Yen Chang, G. Luo, Chao-Ching Cheng, 2009 .

Improved Electrical Characteristics of Bulk FinFETs With SiGe Super-Lattice-Like Buried Channel

G. Luo, Kai-Shin Li, K. Chang-Liao, 2019, IEEE Electron Device Letters.

Experimental Demonstration of (111)-Oriented GaAs Metal–Oxide–Semiconductor Field-Effect-Transistors with Hetero-Epitaxial Ge Source/Drain

G. Luo, C. Ko, C. Chien, 2014 .

Comprehensive Study of Inversion and Junctionless Ge Nanowire Ferroelectric HfZrO Gate-All-Around FETs Featuring Steep Subthreshold Slope with Transient Negative Capacitance

F. Hou, G. Luo, Yung-Chun Wu, 2021 .

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels

G. Huang, C. Hu, F. Hou, 2012, 2012 International Electron Devices Meeting.

First experimental Ge CMOS FinFETs directly on SOI substrate

Chao-Hsin Chien, G. Luo, C. Chien, 2012, 2012 International Electron Devices Meeting.

Schottky Barrier Height Modulation of Metal/n-GeSn Contacts Featuring Low Contact Resistivity by in Situ Chemical Vapor Deposition Doping and NiGeSn Alloy Formation

G. Luo, Y. Chuang, Chia-You Liu, 2021 .

Ultrathin Si capping layer suppresses charge trapping in HfOxNy∕Ge metal-insulator-semiconductor capacitors

Chun-Yen Chang, G. Luo, C. Chien, 2007 .

Fabrication of Si and Ge vertical nanowire for transistor applications

G. Luo, C. Chu, C. Chu, 2015 .

Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement

G. Luo, W. Yeh, C. Chu, 2020, International Symposium on VLSI Technology, Systems, and Applications.

High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET

F. Hou, G. Luo, Yung-Chun Wu, 2023, Nanomaterials.

3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

F. Hou, G. Luo, Yung-Chun Wu, 2023, IEEE Journal of the Electron Devices Society.

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

H. J. Chen, J. Tarng, C. Su, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Electron Mobility Enhancement in GeSn n-Channel MOSFETs by Tensile Strain

G. Luo, Y. Chuang, Jiun-Yun Li, 2020 .

Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance

F. Hou, G. Luo, Yung-Chun Wu, 2021, IEEE Electron Device Letters.

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

T. Hong, P. Sung, K. Kao, 2022, 2022 International Electron Devices Meeting (IEDM).

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

P. Sung, G. Luo, W. Yeh, 2022, 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

FinFET Plus: A Scalable FinFET Architecture with 3D Air-Gap and Air-Spacer Toward the 3nm Generation and Beyond

K. S. Li, G. Luo, E. Hsieh, 2021, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate

J. M. Kowalski, G. Luo, Shih-Chiang Huang, 2009, IEEE Electron Device Letters.

III–V MOSFETs with a new self-aligned contact

Chun-Yen Chang, Xiao Gong, Yee-Chia Yeo, 2010, 2010 Symposium on VLSI Technology.

Ge epitaxial films on GaAs (100), (110), and (111) substrates for applications of CMOS heterostructural integrations

G. Luo, E. Chang, C. Kuo, 2013 .

High quality Ge thin film grown by ultrahigh vacuum chemical vapor deposition on GaAs substrate

Mantu K. Hudait, Edward Yi Chang, Jer-shen Maa, 2011 .

Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs

Yao-Jen Lee, G. Luo, C. Chien, 2016, IEEE Transactions on Electron Devices.