W. Yeh

发表

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Chia-Chen Wan, C. Wang, C. Su, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators

C. Hu, W. Yeh, W. Lo, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Hot Electron Effect on FinFET RF Circuit Reliability

W. Yeh, Jiann-Shiun Yuan, C. Xiao, 2014 .

Optimum halo structure for sub-0.1 /spl mu/m CMOSFETs

W. Yeh, J. Chou, 2001 .

a-SiGeC thin film photovoltaic enabled self-power monolithic 3D IC under indoor illumination

W. Yeh, Meng-Fan Chang, C. Shen, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET

Po-Ying Chen, Wen-Kuan Yeh, Kwang-Jow Gan, 2016, IEEE Transactions on Device and Materials Reliability.

Ge GAA FETs and TMD FinFETs for the Applications Beyond Si—A Review

Jia-Min Shieh, Chih-Chao Yang, Chang-Hong Shen, 2016, IEEE Journal of the Electron Devices Society.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

Chenming Hu, Yi-Ju Chen, Lain-Jong Li, 2014, 2014 IEEE International Electron Devices Meeting.

The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs

Wen-Kuan Yeh, Chien-Ting Lin, Chieh-Ming Lai, 2006, IEEE Transactions on Electron Devices.

The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

W. Yeh, F. Huang, Yu-Ting Chen, 2010, IEEE Electron Device Letters.

Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing

T. C. Huang, P. Yu, W. Yeh, 2017 .

Hot-Carrier-induced Degradation on 0.1μm Partially Depleted SOI CMOSFET with thin Oxide

W. Yeh, Fu-Liang Yang, Y. Fang, 2002 .

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

W. Yeh, K. Gan, Jeng-Jong Lu, 2016 .

A novel sacrificial gate stack process for suppression of boron penetration in p-MOSFET with shallow BF/sub 2/-implanted source/drain extension

Chun-Yen Chang, T. Chao, W. Yeh, 2000 .

Efficient Suppression of Substrate Noise Coupling in CMOS Technology

W. Yeh, Y. Fang, C. Lai, 2003 .

Light emission from the porous boron δ-doped Si superlattice

G. Huang, Chun-Yen Chang, W. Yeh, 1996 .

A Rapid Screening Test for the Diagnosis of Influenza Infection Incubation Period Using Coincidence Analysis of Pulse Waves

W. Yeh, Po-Ying Chen, Shyr-Shen Yu, 2017 .

Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping

Chao-Hsin Chien, Wen-Kuan Yeh, Yu-Hsien Lin, 2017, IEEE Transactions on Electron Devices.

Thermal stability of AlSiCu/W/n(+)p diodes with and without TiN barrier layer

W. Yeh, Mou‐shiung Lin, Mao-chieh Chen, 1995 .

Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

C. Hu, W. Yeh, Kuan-Neng Chen, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Back bias modulation of UTBB FDSOI, bulk FinFET, and SOI FinFET

W. Yeh, W. Chang, Shih-Wei Lin, 2016, 2016 IEEE International Nanoelectronics Conference (INEC).

3D-TCAD simulation study of the contact all around T-FinFET structure for 10nm metal-oxide-semiconductor field-effect transistor

W. Yeh, S. Chung, C. Chien, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Terahertz Schottky barrier diodes with various isolation designs for advanced radio frequency applications

W. Yeh, C. Chao, Y. Fang, 2010 .

Trap induced negative differential conductance and back-gated charge redistribution in AlGaN/GaN power devices

W. Yeh, P. Shea, Balakrishnan Krishnan, 2019, Microelectronics Reliability.

Piezoresistive sensor of short- and long- channel MOSFETs on (100) silicon

W. Yeh, W. Chang, Jian-an Lin, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Effect of $\hbox{NH}_{3}$ Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-$ \kappa$ Dielectric nMOSFETs

Kun-Ming Chen, G. Huang, W. Yeh, 2011, IEEE Transactions on Electron Devices.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

Kang L. Wang, W. Yeh, Y. Su, 2017, ACS nano.

Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC

W. Yeh, C. Shen, J. Shieh, 2016, 2016 IEEE Symposium on VLSI Technology.

Microstructure and piezoelectric properties of reactively sputtered highly C-axis ScxAl1-xN thin films on diamond-like carbon/Si substrate

W. Yeh, Jow-Lay Huang, Sean Wu, 2016 .

The Impact of Junction Doping Distribution on Device Performance Variability and Reliability for Fully Depleted Silicon on Insulator With Thin Box Layer MOSFETs

W. Yeh, Jiann-Shiun Yuan, Cheng-li Lin, 2015, IEEE Transactions on Nanotechnology.

Characterization and modeling of SOI varactors at various temperatures

Kun-Ming Chen, G. Huang, W. Yeh, 2004, Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442).

The New Concept for Particle Remove in Wet Bench Cleaning

W. Yeh, Shen-Li Chen, S. Chen, 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Device Characteristics of E-mode GaN HEMTs with a Second Gate Connected to the Source

J. Shieh, W. Yeh, C. Shen, 2020, Journal of Electronic Materials.

AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition

Chun-Yen Chang, J. Shieh, W. Yeh, 2017, Nanoscale Research Letters.

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

W. Yeh, Fu-Liang Yang, Y. Fang, 2002 .

Impact of SOI Thickness on FUSI-Gate CESL CMOS Performance and Reliability

Kun-Ming Chen, W. Yeh, Jiann-Shiun Yuan, 2011, IEEE Transactions on Device and Materials Reliability.

Comprehensive device reliability and oxide traps distribution analysis by the low frequency noise in ultra-thin body SOI (UTBSOI) MOSFETs

W. Yeh, Wei-Yi Chang, Cheng-li Lin, 2013, 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC).

An experimental investigation of current stressing on wafer-level chip-scale packages

Yi-Shao Lai, Wen-Kuan Yeh, Po-Ying Chen, 2006, 2006 8th Electronics Packaging Technology Conference.

Chemical mechanical polishing for selective CVD-W

L. J. Chen, W. Yeh, W. Tseng, 1997 .

An Efficient Improvement for Barrier Effect of W-filled Contact

M. Tsai, W. Yeh, S. Chen, 1995 .

Dynamic scanning method to clarify the mechanism of WLCSP package reliability issue

Shen-Li Chen, Chwei-Shyong Tsai, Po-Ying Chen, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Elucidating the Effects of Current Stress History on Reliability Characteristics by Dynamic Analysis

Shen-Li Chen, Po-Ying Chen, Wen-Kuan Yeh, 2008 .

Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

W. Yeh, Y. Lai, Po-Ying Chen, 2008 .

The effect of stressing history in reliability characteristics

Yi-Shao Lai, Wen-Kuan Yeh, Po-Ying Chen, 2006, 2006 8th Electronics Packaging Technology Conference.

Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

Wen-Shiang Liao, Wen-Kuan Yeh, Han-Wen Liu, 2013, IEEE Transactions on Electron Devices.

Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs

Kun-Ming Chen, G. Huang, C. Hu, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Strain-Induced Ionic Polarization Dependent AlGaN/GaN High Electron Mobility Transistor

W. Yeh, D. Nirmal, N. Kumar, 2020, 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184).

Sub-60mV-swing negative-capacitance FinFET without hysteresis

Chenming Hu, Sayeef Salahuddin, Kai-Shin Li, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology

Yao-Jen Lee, P. Sung, W. Yeh, 2021, 2021 Symposium on VLSI Technology.

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

S. Burc Eryilmaz, Min-Cheng Chen, Jia-Min Shieh, 2016, 2016 IEEE Symposium on VLSI Technology.

Monolithic 3D+-IC Based Massively Parallel Compute-in-Memory Macro for Accelerating Database and Machine Learning Primitives

Hariram Thirucherai Govindarajan, Srivatsa Srinivasa Rangachar, J. Sampson, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Dual-mode operation of 2D material-base hot electron transistors

Kang L. Wang, J. R. Adleman, W. Yeh, 2016, Scientific Reports.

Atomic-Monolayer MoS2 Band-to-Band Tunneling Field-Effect Transistor.

Kang L. Wang, W. Yeh, Lain‐Jong Li, 2016, Small.

Electromigration reliability of dual damascene Cu/CVD SiOC interconnects

R. Augur, M. Tsai, W. Yeh, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Deposition properties of selective tungsten chemical vapor deposition

W. Yeh, Mou‐shiung Lin, Mao-chieh Chen, 1996 .

Selective tungsten CVD on submicron contact hole

W. Yeh, Mou‐shiung Lin, Mao-chieh Chen, 1995 .

Logic/memory hybrid 3D sequentially integrated circuit using low thermal budget laser process

Meng-Fan Chang, Chih-Chao Yang, Jia-Min Shieh, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Using Capacitance Sensor to Extract Characteristic Signals of Dozing from Skin Surface

Chi-Chang Chen, Yu-Jung Huang, Shyr-Shen Yu, 2014, J. Sensors.

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

G. Huang, Yao-Jen Lee, F. Hou, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

W.-F. Wu, C. Wang, C. Su, 2017, 2017 Symposium on VLSI Technology.

Stacked Ge-Nanosheet GAAFETs Fabricated by Ge/Si Multilayer Epitaxy

G. Luo, W. Yeh, C. Chu, 2018, IEEE Electron Device Letters.

Relationship between wafer edge design and its ultimate mechanical strength

M. Tsai, W. Yeh, Po-Ying Chen, 2010 .

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

M. Tsai, W. Yeh, Po-Ying Chen, 2010 .

Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

M. Tsai, W. Yeh, Po-Ying Chen, 2009 .

Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes

T. C. Huang, W. Yeh, C. Shen, 2016 .

A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

W. Yeh, Chien-Ting Lin, M. Ma, 2007, IEEE Electron Device Letters.

3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

C. Yao, C. Su, T. Hong, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

TSV-free FinFET-based Monolithic 3D+-IC with computing-in-memory SRAM cell for intelligent IoT devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment

C. J. Wang, C. Su, T. Hong, 2018, IEEE Journal of the Electron Devices Society.

Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs

Shih-Wei Lin, Wen-Kuan Yeh, W. Yeh, 2018, IEEE Transactions on Nanotechnology.

Low-Leakage Tetragonal ZrO2 (EOT < 1 nm) With In Situ Plasma Interfacial Passivation on Germanium

W. Yeh, C. Chien, C. Chou, 2016, IEEE Electron Device Letters.

Footprint-efficient and power-saving monolithic IoT 3D+ IC constructed by BEOL-compatible sub-10nm high aspect ratio (AR>7) single-grained Si FinFETs with record high Ion of 0.38 mA/μm and steep-swing of 65 mV/dec. and Ion/Ioff ratio of 8

Jia-Min Shieh, Chih-Chao Yang, Chang-Hong Shen, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing

Chun-Yu Chen, Chia-Wei Hsu, Yean-Kuen Fang, 2010, Microelectron. Reliab..

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

P. Sung, K. Kao, Y. Lee, 2014, 2014 IEEE International Electron Devices Meeting.

High Gamma Value 3D-Stackable HK/MG-Stacked Tri-Gate Nanowire Poly-Si FETs With Embedded Source/Drain and Back Gate Using Low Thermal Budget Green Nanosecond Laser Crystallization Technology

W. Yeh, C. Shen, J. Shieh, 2016, IEEE Electron Device Letters.

RF stress effects on CMOS LC-loaded VCO reliability evaluated by experiments

J. S. Yuan, H. D. Yen, R. L. Wang, 2012, Microelectron. Reliab..

Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process

W. Yeh, Chien-Ting Lin, Chieh-Ming Lai, 2007 .

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Guo-Wei Huang, Tuo-Hung Hou, Tien-Sheng Chao, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Voltage-controlled multiple-valued logic design using negative differential resistance devices

Wen-Kuan Yeh, Kwang-Jow Gan, Cher-Shiung Tsai, 2010 .

The Improvement of High-$k$/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

W. Yeh, K. Gan, F. Huang, 2011, IEEE Transactions on Device and Materials Reliability.

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

W. Yeh, Ping-Yi Hsieh, C. Shen, 2020, Micromachines.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

J. Tarng, Kun-Ming Chen, G. Huang, 2022, IEEE Transactions on Electron Devices.

Design and application of Van Der Pol oscillator using NDR circuit

Wen-Kuan Yeh, Cher-Shiung Tsai, Kwang-Jow Gan, 2013, 2013 International Symposium on Next-Generation Electronics.

Investigation of AlGaN/GaN HEMT Breakdown analysis with Source field plate length for High power applications

Arivazhagan L, Godfrey D, D Nirmal, 2020, 2020 5th International Conference on Devices, Circuits and Systems (ICDCS).

Effect of Nitrogen Incorporation in a Gd Cap Layer on the Reliability of Deep-Submicrometer Hf-Based High-$k$/Metal-Gate nMOSFETs

W. Yeh, C. Lai, Chia-Wei Hsu, 2009, IEEE Electron Device Letters.

Temperature dependence of hot-carrier-induced degradation in 0.1 μm SOI nMOSFETs with thin oxide

Fu-Liang Yang, Wen-Kuan Yeh, Wen-Han Wang, 2002 .

Damage-Free ALD Blocking Oxide Layer on Functionalized Graphene Nanosheets as Nonvolatile Memories

W. Yeh, Kai-Shin Li, Han-Hsiang Tai, 2019, IEEE Transactions on Electron Devices.

A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS2 FET

C. Hu, W. Yeh, Tahui Wang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Impact of Fin Width and Back Bias Under Hot Carrier Injection on Double-Gate FinFETs

Wen-Kuan Yeh, W. Yeh, W. Chang, 2015, IEEE Transactions on Device and Materials Reliability.

The Impact of Strain Technology on FUSI Gate SOI CMOSFET

M. Tsai, W. Yeh, Po-Ying Chen, 2009 .

Enhancement of DC and Breakdown Performance on Single to Multi-Step Gate FP Using GaN-HEMT for High Power Applications

W. Yeh, N. Mohankumar, D. Nirmal, 2020, Silicon.

MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability

Jia-Min Shieh, Yu-Lun Chueh, Chenming Hu, 2016, 2016 IEEE Symposium on VLSI Technology.

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

C. Wang, C. Su, P. Sung, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement

G. Luo, W. Yeh, C. Chu, 2020, International Symposium on VLSI Technology, Systems, and Applications.

Study on device reliability for P-type FinFETs with different fin numbers

W. Yeh, Wenqi Zhang, Yi-Lin Yang, 2020 .

CiM3D: Comparator-in-Memory Designs Using Monolithic 3-D Technology for Accelerating Data-Intensive Applications

Jia-Min Shieh, Jack Sampson, Cheng-Xin Xue, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

The Impact of Fin Number on Device Performance and Reliability for Multi-Fin Tri-Gate n- and p-Type FinFET

W. Yeh, Wenqi Zhang, Yi-Lin Yang, 2018, IEEE Transactions on Device and Materials Reliability.

Influence of fin number on hot-carrier injection stress induced degradation in bulk FinFETs

Wenqi Zhang, Wen-Kuan Yeh, Shih-Yao Chen, 2016, Microelectron. Reliab..

Study on Intrinsic Hot Carrier Degradation of FinFETs with Different Stress Conditions and Fin Numbers by Decoupling PBTI Component

W. Yeh, Wenqi Zhang, Yi-Lin Yang, 2020 .

Examination of hot-carrier stress induced degradation on fin field-effect transistor

W. Yeh, Tai-Hsuan Wu, Wenqi Zhang, 2014 .

Study on interfacial trap location induced subthreshold slope degradation extracted by random telegraph noise for high-k/metal gate FinFET devices

W. Yeh, Wenqi Zhang, Yi-Lin Yang, 2020 .

Reliability Improvement of 28-nm High-$k$ /Metal Gate-Last MOSFET Using Appropriate Oxygen Annealing

W. Yeh, C. Lai, Chia-Wei Hsu, 2012, IEEE Electron Device Letters.

A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications

Meng-Fan Chang, Guo-Wei Huang, Hiroyuki Yamauchi, 2018, IEEE Electron Device Letters.

Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

W. Yeh, K. Gan, Cher-Shiung Tsai, 2011 .

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Jia-Min Shieh, Chenming Hu, Wen-Cheng Chiu, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+ -IC with Computing-in-Memory for Intelligent IoT Devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

H. J. Chen, J. Tarng, C. Su, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

P. Sung, G. Luo, W. Yeh, 2022, 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Yao-Jen Lee, C. Hu, W. Yeh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

C. Su, K. Kao, Y. Tang, 2019, Symposium on VLSI Technology.

Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

W. Yeh, Chien-Ting Lin, M. Ma, 2006, IEEE Electron Device Letters.

C-V Measurement under Different Frequencies and Pulse-mode Voltage Stress to Reveal Shallow and Deep Trap Effects of GaN HEMTs

W. Yeh, Jiann-Shiun Yuan, Balakrishnan Krishnan, 2018, 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA).

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

Meng-Fan Chang, Guo-Wei Huang, Ting-Jen Hsueh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro

Kun-Ming Chen, G. Huang, C. Hu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Reliability Performance of a 70-GHz Mixer in 65-nm Technology

H.-D Yen, J.-S Yuan, G.-W Huang, 2016, IEEE Transactions on Device and Materials Reliability.