J. Cai

A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time

W. Luk, J. Cai, R. Dennard, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

Low power circuit design based on heterojunction tunneling transistors (HETTs)

David Blaauw, Dennis Sylvester, Daeyeon Kim, 2009, ISLPED.

Toward Ultimate Scaling of MOSFET

J. Cai, D. Frank, R. Muralidhar, 2016, IEEE Transactions on Electron Devices.

Monitoring interface traps by DCIV method

J. Cai, C. Sah, Jin Cai, 1999 .

On the Performance and Scaling of Symmetric Lateral Bipolar Transistors on SOI

Jin Cai, T. H. Ning, J. Cai, 2013, IEEE Journal of the Electron Devices Society.

Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors

Jin Cai, Chih-Tang Sah, J. Cai, 2001 .

Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs

Jin Cai, P. Oldiges, I. Lauer, 2013, IEEE Transactions on Electron Devices.

Comparison of large-scale layer-relaxation simulations with experiment

J. Cai, P. Mooney, K. Schwarz, 2004 .

Analysis and modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs

J. Cai, W. Haensch, K. Rim, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).