Marius Strum

发表

Burst-Mode Asynchronous Controllers on FPGA

Duarte Lopes de Oliveira, Marius Strum, Sandro S. Sato, 2008, Int. J. Reconfigurable Comput..

Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor

Jiang Chau Wang, Marius Strum, Edgar Leonardo Romero Tobar, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification

Jiang Chau Wang, Marius Strum, Edgar Leonardo Romero Tobar, 2013, J. Electron. Test..

Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS

Jiang Chau Wang, Marius Strum, Raul Acosta Hernandez, 2015, 2015 16th Latin-American Test Symposium (LATS).

Pseudoexhaustive test techniques: a new algorithm to partition combinational networks

Marius Strum, José Roberto Amazonas, J. Amazonas, 1989, [1989] Proceedings of the 1st European Test Conference.

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

A Recursive High Level Synthesis System

Jiang Chau Wang, Marius Strum, M. Y. Teruya, 1997 .

TSV protection: Towards secure 3D-MPSoC

Martha Johanna Sepúlveda, Guy Gogniat, Jean-Philippe Diguet, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

Workload and task characterization based on operation modes timing analysis

Jiang Chau Wang, Marius Strum, Jorge Gonzalez, 2012, 2012 IEEE International SOC Conference.

A System-level Performance Evaluation Methodology for Netwrok Processors Based on Network Calculus Analytical Modeling

Jiang Chau Wang, Marius Strum, Frederico De Faria, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Formally verifying an RTOS scheduling monitor IP core in embedded systems

Fabian Vargas, Marius Strum, Wang Jiang Chau, 2011, 2011 12th Latin American Test Workshop (LATW).

A general-purpose dynamically reconfigurable SVM

Marius Strum, Wang Jiang Chau, Jonas Gomes Filho, 2010, 2010 VI Southern Programmable Logic Conference (SPL).

A multi-objective approach for multi-application NoC mapping

Guy Gogniat, Johanna Sepulveda, Marius Strum, 2011, 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS).

Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection

Martha Johanna Sepúlveda, Jiang Chau Wang, Ricardo Pires, 2010, Trans. Comput. Sci..

Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2013, 2013 8th IEEE Design and Test Symposium.

Support vector machine coverage driven verification for communication cores

Marius Strum, Wang Jiang Chau, Edgar Romero, 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

Hybrid-on-chip communication architecture for dynamic MP-SoC protection

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2012, 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI).

Dynamic NoC-based architecture for MPSoC security implementation

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2011, SBCCI '11.

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems

Jiang Chau Wang, Marius Strum, Jonas Gomes Filho, 2015, Int. J. Reconfigurable Comput..

Miriã_SI: A Tool for the Synthesis of Speed-Independent Multi Burst-Mode Controllers

Jiang Chau Wang, Duarte Lopes de Oliveira, Marius Strum, 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

Power management exploration for a block turbo decoder

Marius Strum, João Martins, 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training

Jiang Chau Wang, Marius Strum, Raul Acosta Hernandez, 2009, 2009 International Joint Conference on Neural Networks.

Elastic security zones for NoC-based 3D-MPSoCs

Martha Johanna Sepúlveda, Guy Gogniat, Jean-Philippe Diguet, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A PD-based methodology to enhance efficiency in testbenches with random stimulation

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2009, SBCCI.

A placement tool for a NOC-based dynamically reconfigurable system

Marius Strum, Wang Jiang Chau, Jonas Gomes Filho, 2010, 2010 VI Southern Programmable Logic Conference (SPL).

A Multi-objective Adaptive Immune Algorithm for NoC mapping

Marius Strum, M. Johanna Sepulveda, Wang J. Chau, 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2012, Int. J. Reconfigurable Comput..

SINMEF-a decomposition based synthesis tool for large FSMs

Carlos H. Llanos, Marius Strum, C. Llanos, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

The LRD traffic impact on the NoC-based SoCs

Martha Johanna Sepúlveda, Jiang Chau Wang, Ricardo Pires, 2010, SBCCI '10.

PrOCov: Probabilistic output coverage model

Jiang Chau Wang, Marius Strum, Joel Ivan Munoz Quispe, 2013, 2013 14th Latin American Test Workshop - LATW.

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Guy Gogniat, Marius Strum, Wang Jiang Chau, 2012 .

A methodology for minimum area cellular automata generation

Jiang Chau Wang, Marius Strum, José Roberto de A. Amazonas, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Scalable NoC-based architecture of neural coding for new efficient associative memories

Martha Johanna Sepúlveda, Jean-Philippe Diguet, Nicolas Le Griguer, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Formal equivalence checking between high-level and RTL hardware designs

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2013, 2013 14th Latin American Test Workshop - LATW.

Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems

Jiang Chau Wang, Duarte Lopes de Oliveira, Marius Strum, 2003, Microelectron. Reliab..

Architectural Transformations for Hierarchical Algorithmic Descriptions

Jiang Chau Wang, Marius Strum, Marcio Yukio Teruya, 1999, VLSI.

Data path functional unites BIST plan optimization

Bruno Rouzeyre, Marius Strum, José Roberto Amazonas, 1997 .

Exploring Models of Computation through Static Analysis

Marius Strum, Ivan Jeukens, 2003, FDL.

Comparison between quasi-uniform linear cellular automata and linear feedback shift registers as test pattern generators for built-in self-test applications

Marius Strum, Wang Jiang Chau, J. R. de A. Amazonas, 1999, Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387).

A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2015, J. Electron. Test..

A dynamically reconfigurable Bluetooth Base Band Unit

Jiang Chau Wang, Marius Strum, John Esquiagola, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Automatic generation of a parameter-domain-based functional input coverage model

Marius Strum, Wang Jiang Chau, Carlos Ivan Castro, 2010, 2010 11th Latin American Test Workshop.

Transformations for functional modules in hierarchical high level synthesis

Jiang Chau Wang, Marius Strum, A A Jerraya, 1997 .

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Jiang Chau Wang, Marius Strum, Edgar Leonardo Romero Tobar, 2011, J. Electron. Test..

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2012, GECCO '12.

3D-LeukoNoC: A Dynamic TSV-Based 3D-MPSoC Protection

Guy Gogniat, Jean-Philippe Diguet, Marius Strum, 2014, ReConFig 2014.

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

NoC-Based Protection for SoC Time-Driven Attacks

Martha Johanna Sepúlveda, Guy Gogniat, Jean-Philippe Diguet, 2015, IEEE Embedded Systems Letters.

A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2014, 2014 15th Latin American Test Workshop - LATW.

Exploring concurrency in data path functional units BIST plan optimization: a study-case

Marius Strum, Wang Jiang Chau, José Roberto de A. Amazonas, 1998, Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216).

A strategy for recursive high level synthesis

Jiang Chau Wang, Marius Strum, A A Jerraya, 1997 .

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2013, GECCO '13 Companion.

3D-LeukoNoC: A dynamic NoC protection

Martha Johanna Sepúlveda, Guy Gogniat, Jean-Philippe Diguet, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

Synthesis of Concurrent Asynchronous State Machines Using Extended Multi-Burst Graph Specification

Marius Strum, Wang Jiang Chau, Duarte Lopes de Oliveira, 2006 .