S. Satoh

发表

Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems

Y. Tosaka, H. Kanata, T. Itakura, 1999 .

Cosmic ray neutron-induced soft errors in sub-half micron CMOS circuits

Y. Tosaka, T. Itakura, S. Satoh, 1997, IEEE Electron Device Letters.

Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's

Y. Tosaka, S. Satoh, S. Wender, 2000, IEEE Electron Device Letters.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

N. Horiguchi, T. Yamamoto, S. Satoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

S. Satoh, S. Pidin, T. Mori, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Alpha-particle-induced collected charge model in SOI-DRAM's

Yoshiharu Tosaka, Shigeo Satoh, Y. Tosaka, 1999 .

Measurements and analysis of neutron-reaction-induced charges in a silicon surface region

Toshihiro Sugii, Yoshiharu Tosaka, Shigeo Satoh, 1997 .

Carrier profile designing to suppress systematic Vth variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects

S. Satoh, H. Minakata, Y. Momiyama, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Neutron-Induced Soft-Error Simulation Technology for Logic Circuits

Taiki Uemura, Yoshiharu Tosaka, Shigeo Satoh, 2006 .

High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects

Tomohiro Kubo, Mitsuru Yamaji, S. Satoh, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors

Tetsu Tanaka, Shigeo Satoh, Satoshi Ando, 1993 .

Three-dimensional simulation of scanning tunneling microscopy for semiconductor carrier and impurity profiling

S. Satoh, Kunihiro Suzuki, K. Fukuda, 2014 .

First Quantitative Observation of Local Temperature Fluctuation in Millisecond Annealing

S. Satoh, T. Yamamoto, T. Sukegawa, 2007, 2007 15th International Conference on Advanced Thermal Processing of Semiconductors.

CMOS-SRAM soft-error simulation system

S. Satoh, R. Sudo, H. Tashiro, 1994, Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V.

Mechanical Stress Evaluation of Si Metal–Oxide–Semiconductor Field-Effect Transistor Structure Using Polarized Ultraviolet Raman Spectroscopy Measurements and Calibrated Technology-Computer-Aided-Design Simulations

S. Satoh, H. Arimoto, T. Tada, 2011 .

Impact of cosmic ray neutron induced soft errors on advanced submicron CMOS circuits

T. Sugii, S. Satoh, H. Ehara, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal–Oxide–Semiconductor Field Effect Transistor with Embedded SiGe

Taiki Uemura, S. Satoh, Y. Ikeda, 2013 .

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

S. Satoh, T. Sugii, H. Ohta, 2007, 2007 IEEE International Electron Devices Meeting.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

S. Satoh, Y. Momiyama, S. Satoh, 2010, IEEE Electron Device Letters.