J. Teich

Hardware Cost Analysis for Weakly Programmable Processor Arrays

D. Kissler, F. Hannig, A. Kupriyanov, 2006, 2006 International Symposium on System-on-Chip.

Session details: System synthesis

J. Teich, P. Pop, 2008, DATE '08.

A system-level approach to hardware reconfigurable systems

J. Teich, C. Haubelt, S. Otto, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Run time mapping of adaptive applications onto homogeneous NoC-based reconfigurable architectures

J. Teich, S. Wildermann, T. Ziermann, 2009, 2009 International Conference on Field-Programmable Technology.

A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs

J. Teich, C. Haubelt, C. Zebelein, 2012, 2012 Electronic System Level Synthesis Conference.

Online hardware/software partitioning in networked embedded systems

J. Teich, C. Haubelt, T. Streichert, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..