H. Byun

A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

Kinam Kim, Y. Hwang, G. Koh, 2005, IEEE Journal of Solid-State Circuits.

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

Kinam Kim, Y. Hwang, Beak-Hyung Cho, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Byung-Gil Choi, Hongsik Jeong, Chang-Soo Lee, 2007, IEEE Journal of Solid-State Circuits.

SMD-based internal clock generator for memory test

Nam-Seog Kim, Hyo-Chang Kim, Hyun-Guen Byun, 2005 .

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

Young-Hyun Jun, Kyomin Sohn, Young-Ho Suh, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Scalable Two Transistor Memory (STTM) for mobile embedded applications with 80nm technology

Byung-Gil Choi, Woo Yeong Cho, Beak-Hyung Cho, 2004 .