J. Bahn

A Generic Traffic Model for On-Chip Interconnection Networks

J. Bahn, Qualcomm, 2008 .

WINTER 07 Project Name : A Multi-Processor Architecture for Multimode Mobile Digital TV Platforms CPCC Affiliate

J. Bahn, N. Bagherzadeh, A. Eltawil, 2007 .

FALL 06 Project Name : A Multi-Processor Architecture for Multimode Mobile Digital TV Platforms CPCC Affiliate

J. Bahn, N. Bagherzadeh, A. Eltawil, 2007 .

On-Chip Interconnection Network with an E cient Parallel Bu er Structure and Generic Tra c Model

J. Bahn, N. Bagherzadeh, 2009 .

Parallel FFT Algorithms on Network-on-Chips

Wen-Hsiang Hu, Nader Bagherzadeh, Jun Ho Bahn, 2008, Fifth International Conference on Information Technology: New Generations (itng 2008).

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)

Seung Eun Lee, Nader Bagherzadeh, Jun Ho Bahn, 2007, 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07).

Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform

Nader Bagherzadeh, Jun Ho Bahn, W.-H. Hu, 2012, IET Comput. Digit. Tech..

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform

Wen-Hsiang Hu, Nader Bagherzadeh, Jun Ho Bahn, 2009, 2009 21st International Symposium on Computer Architecture and High Performance Computing.