G. Braun

A novel approach for flexible and consistent ADL-driven ASIP design

Rainer Leupers, Heinrich Meyr, Weihua Sheng, 2004, Proceedings. 41st Design Automation Conference, 2004..

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2004, SAMOS.

A universal technique for fast and flexible instruction-set architecture simulation

G. Braun, A. Nohl, R. Leupers, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Retargetable compilers and architecture exploration for embedded processors

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2005 .

A methodology and tool suite for C compiler generation from ADL processor models

Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

RTL processor synthesis for architecture exploration and implementation

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Instruction encoding synthesis for architecture exploration using hierarchical processor models

Rainer Leupers, Heinrich Meyr, Andreas Hoffmann, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

A universal technique for fast and flexible instruction-set architecture simulation

Rainer Leupers, Heinrich Meyr, Andreas Hoffmann, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2003, SCOPES.