M. Koyanagi

发表

Relation between hot-carrier light emission and kink effect in poly-Si thin film transistors

M. Koyanagi, H. Kurino, T. Hashimoto, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits

M. Koyanagi, Tetsu Tanaka, T. Konno, 2010 .

A Cavity Chip Interconnection Technology for Thick MEMS Chip Integration in MEMS-LSI Multichip Module

M. Koyanagi, Kang-wook Lee, S. Kanno, 2010, Journal of Microelectromechanical Systems.

Flux-assisted self-assembly with microbump bonding for 3D heterogeneous integration

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

M. Koyanagi, T. Fukushima, T. Tanaka, 2012, 2012 International Electron Devices Meeting.

Characterization of 3D stacked high resistivity Si interposers with polymer TSV liners for 3D RF module

M. Koyanagi, Kang-wook Lee, Y. Eom, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

M. Koyanagi, Tetsu Tanaka, T. Fukushima, 2016 .

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

M. Koyanagi, H. Kurino, Tetsu Tanaka, 2006, IEEE Transactions on Electron Devices.

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

M. Koyanagi, T. Fukushima, K. Lee, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

M. Koyanagi, T. Hattori, H. Nohira, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

M. Koyanagi, H. Nohira, T. Fukushima, 2010, 2010 International Electron Devices Meeting.

Minimizing the local deformation induced around Cu-TSVs and CuSn/InAu-microbumps in high-density 3D-LSIs

M. Koyanagi, T. Fukushima, T. Tanaka, 2012, 2012 International Electron Devices Meeting.

Impacts of static and dynamic local bending of thinned Si chip on MOSFET performance in 3-D stacked LSI

M. Koyanagi, T. Fukushima, K. Lee, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

M. Koyanagi, K. Kiyoyama, T. Tanaka, 2013, 2013 IEEE International Interconnect Technology Conference - IITC.

Three-dimensional integration technology for sensor application using 5-µm-pitch au cone bump connections

M. Koyanagi, M. Aoyagi, M. Motoyoshi, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

M. Koyanagi, Tetsu Tanaka, T. Fukushima, 2016 .

New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

M. Koyanagi, T. Fukushima, Y. Yamada, 2006 .

Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Direct multichip-to-wafer 3D integration technology using flip-chip self-assembly of NCF-covered known good dies

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2015 .

Capillary Self-Assembly for 3D Heterogeneous System Integration and Packaging

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2016 .

Transfer and Non-transfer 3D Stacking Technologies Based on Multichip-to-Wafer Self-Assembly and Direct Bonding

M. Koyanagi, T. Fukushima, T. Tanaka, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Low-Loss Optical Interposer with Recessed Vertical-Cavity Surface-Emitting Laser Diode and Photodiode Chips into Si Substrate

M. Koyanagi, Tetsu Tanaka, Y. Shirato, 2008 .

Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing

M. Koyanagi, Kang-wook Lee, E. Iwata, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Multichip-to-Wafer Three-Dimensional Integration Technology Using Chip Self-Assembly With Excimer Lamp Irradiation

M. Koyanagi, E. Iwata, T. Fukushima, 2012, IEEE Transactions on Electron Devices.

Reductant-Assisted Self-Assembly with Cu/Sn Microbump for Three-Dimensional Heterogeneous Integration

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2013 .

Applications of three-dimensional LSI

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2015 .

Study of Vacuum-Assisted Spin Coating of Polymer Liner for High-Aspect-Ratio Through-Silicon-Via Applications

M. Koyanagi, Kang-wook Lee, T. Fukushima, 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Three-Dimensionally Stacked Analog Retinal Prosthesis Chip

M. Koyanagi, H. Kurino, M. Tamai, 2004 .

Through-Silicon Photonic Via and Unidirectional Coupler for High-Speed Data Transmission in Optoelectronic Three-Dimensional LSI

M. Koyanagi, Kang-wook Lee, T. Fukushima, 2012, IEEE Electron Device Letters.

3D LSI and reliability

M. Koyanagi, 2011, 18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

Three-Diensional Integration Technology Based on Wafer Bonding Technique Using Micro-Bumps

M. Koyanagi, T. Matsumoto, Y. Kudoh, 1995 .

New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method.

M. Koyanagi, H. Kurino, K. Sakuma, 1998 .

Self-assembly technology for reconfigured wafer-to-wafer 3D integration

M. Koyanagi, T. Fukushima, E. Iwata, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

M. Koyanagi, Kang-wook Lee, T. Fukushima, 2011, IEEE Electron Device Letters.

A new temporary bonding technology with spin-on glass and hydrogenated amorphous Si for 3D LSIs

M. Koyanagi, K. Lee, T. Fukushima, 2014, 2014 International Conference on Electronics Packaging (ICEP).

A New Wafer Scale Chip-on-Chip (W-COC) Packaging Technology Using Adhesive Injection Method

M. Koyanagi, H. Kurino, K. Sakuma, 1999 .

Self-Assembly Process for Chip-to-Wafer Three-Dimensional Integration

M. Koyanagi, T. Fukushima, T. Tanaka, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

High density 3D LSI technology using W/Cu hybrid TSVs

M. Koyanagi, T. Fukushima, T. Tanaka, 2011, International Electron Devices Meeting.

Self-assembly technologies with high-precision chip alignment and fine-pitch microbump bonding for advanced die-to-wafer 3D integration

M. Koyanagi, K. Lee, T. Fukushima, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Non-conductive film and compression molding technology for self-assembly-based 3D integration

M. Koyanagi, T. Fukushima, T. Tanaka, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

3D integration technology and reliability

M. Koyanagi, 2011, 2011 International Reliability Physics Symposium.

High-step-coverage Cu-lateral interconnections over 100 µm thick chips on a polymer substrate—an alternative method to wire bonding

M. Koyanagi, Tetsu Tanaka, Jichoel Bea, 2012 .

3D-LSI technology for image sensor

M. Koyanagi, M. Motoyoshi, 2009 .

Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2014, IEEE Transactions on Electron Devices.

Development of highly-reliable microbump bonding technology using self-assembly of NCF-covered KGDs and multi-layer 3D stacking challenges

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

A simple device allowing silicon microelectrode insertion for chronic neural recording in primates

H. Mushiake, K. Sakamoto, M. Koyanagi, 2009, 2009 4th International IEEE/EMBS Conference on Neural Engineering.

Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2008 .

Impacts of Cu Contamination on Device Reliabilities in 3-D IC Integration

Mitsumasa Koyanagi, Takafumi Fukushima, Mariappan Murugesan, 2014, IEEE Transactions on Device and Materials Reliability.

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

M. Koyanagi, K. Kiyoyama, H. Hashimoto, 2012, 2012 International Electron Devices Meeting.

Development of Si neural probe with optical waveguide for highly accurate optical stimulation of neuron

M. Koyanagi, R. Kobayashi, M. Koyanagi, 2011, 2011 5th International IEEE/EMBS Conference on Neural Engineering.

Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emission

M. Koyanagi, H. Kaneko, S. Shimizu, 1985, IEEE Transactions on Electron Devices.

Modelling of Impact Ionization Current for LDD SOI MOSFETs

M. Koyanagi, T. Matsumoto, S. Pidin, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Chip-based hetero-integration technology for high-performance 3D stacked image sensor

Kang Wook Lee, M. Koyanagi, T. Kamada, 2012, 2012 2nd IEEE CPMT Symposium Japan.

Multilevel Charge Storage in a Multiple Alloy Nanodot Memory

Jung Min Lee, M. Koyanagi, Tetsu Tanaka, 2011 .

Characteristics of a Multiple Alloy Nanodot Memory with an Enhanced Charge Storage Capability

M. Koyanagi, Tetsu Tanaka, Y. Song, 2010 .

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

M. Koyanagi, T. Fukushima, T. Fukushima, 2020, Japanese Journal of Applied Physics.

High-bandwidth data transmission of new transceiver module through optical interconnection

Mitsumasa Koyanagi, Takafumi Fukushima, Shinsuke Terada, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs

M. Koyanagi, Tetsu Tanaka, T. Fukushima, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

New Silicon-on-Insulator (SOI) Flash Memory with Side Channel and Side Floating Gate

T. Tanabe, M. Koyanagi, H. Kurino, 2003 .

Effects of fluorocarbon gas species on electrical conductivity and chemical structure of deposited polymer in SiO2 etching processes

M. Koyanagi, K. Hane, S. Samukawa, 2004 .

Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI

Mitsumasa Koyanagi, Takafumi Fukushima, Mariappan Murugesan, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Novel submicrometer MOS devices by self-aligned nitridation of silicide

M. Koyanagi, S. Kishino, Y. Kubota, 1986, IEEE Transactions on Electron Devices.

Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application

M. Koyanagi, Tetsu Tanaka, Y. Pei, 2011 .

Morphological change of Co-nanodot on SiO2 by thermal treatment

M. Koyanagi, H. Kurino, F. Shoji, 2006 .

Small geometry effects in n- and p-channel polysilicon thin film transistors

T. Y. Huang, M. Koyanagi, I. Wu, 1988, Technical Digest., International Electron Devices Meeting.

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

Mitsumasa Koyanagi, Takafumi Fukushima, Mariappan Murugesan, 2014, IEEE Transactions on Electron Devices.

Impact of Interconnections on Vertically Stacked 20 um-Thick DRAM Chips

M. Koyanagi, Tetsu Tanaka, T. Fukushima, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Characterization of Vapor Deposited Polyimides and Process Integration with the Polymeric Liner for Via-Last/Backside-Via Cu-TSV Formation

M. Koyanagi, Kang-wook Lee, T. Fukushima, 2014 .

Via-last/backside-via 3D integration using a visible-light laser debonding technique

M. Koyanagi, M. Motoyoshi, K. Lee, 2014, 2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D).

Cu Retardation Performance of Extrinsic Gettering Layers in Thinned Wafers Evaluated by Transient Capacitance Measurement

M. Koyanagi, Tetsu Tanaka, K. Lee, 2011 .

Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement

M. Koyanagi, Tetsu Tanaka, K. Lee, 2011 .

Development of double-sided Si neural probe with microfluidic channels using wafer direct bonding technique

H. Mushiake, M. Koyanagi, Y. Matsuzaka, 2009, 2009 4th International IEEE/EMBS Conference on Neural Engineering.

Ultimate Functional Multi-Electrode System (UFMES) Based on Multi-Chip Bonding Technique

H. Mushiake, K. Sakamoto, M. Koyanagi, 2004 .

Photon emission from SOI MOSFET with body terminal

M. Koyanagi, Y. Hiruma, Y. Inoue, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Single Chip Integration of LED, Waveguide and Micromirrors

Shin Yokoyama, Mitsumasa Koyanagi, Seiichi Miyazaki, 1994 .

Evaluation of polycrystalline silicon thin film transistors with the charge pumping technique

M. Koyanagi, I. Wu, A. Lewis, 1990, International Technical Digest on Electron Devices.

Evaluation of Electrical Stimulus Current to Retina Cells for Retinal Prosthesis

M. Koyanagi, H. Kurino, E. Sugano, 2005 .

3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2017, IEEE Transactions on Electron Devices.

Retinal Prosthesis Using 3-Dimensional Integration Technology

Mitsumasa Koyanagi, Hiroyuki Kurino, Taiichiro Watanabe, 2003 .

308 Adaptive Vision System with Pulse Frequency Modulation Image Sensor

Jun Deguchi, Mitsumasa Koyanagi, Hiroyuki Kurino, 2004 .

Hot carrier effects in sub-0.1 µm gate length MOSFETs between room and liquid helium temperatures

M. Koyanagi, F. Balestra, T. Matsumoto, 1994 .

Hot Carrier Effects in Sub-0.1 μm MOSFETs

M. Koyanagi, F. Balestra, T. Matsumoto, 1994 .

Kink Effect in 0.1 μm Bulk Si MOSFETs

M. Koyanagi, F. Balestra, T. Matsumoto, 1994 .

A 3-Dimensional Wafer-Level Stacking Technology with Precise Vertical Interconnections to MEMS Applications

K. W. Lee, M. Koyanagi, H. Kurino, 2001 .

Erratum: “A Reliable Nonvolatile Memory Using Alloy Nanodot Layer with Extremely High Density”

M. Koyanagi, Y. Song, Y. Song, 2009 .

Electrical Characterization of Metal–Oxide–Semiconductor Memory Devices with High-Density Self-Assembled Tungsten Nanodots

M. Koyanagi, Tetsu Tanaka, Y. Pei, 2008 .

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

M. Koyanagi, Y. Pei, T. Fukushima, 2011, IEEE Transactions on Nanotechnology.

Vision Chip with Electrical Fovea Motion

M. Koyanagi, J. Deguchi, Y. Nakagawa, 2004 .

Investigation of the effect of in situ annealing of FePt nanodots under high vacuum on the chemical states of Fe and Pt by x-ray photoelectron spectroscopy

M. Koyanagi, T. Hattori, H. Nohira, 2008 .

Magnetic characteristics of FePt nanodots formed by a self-assembled nanodot deposition method

M. Koyanagi, Tetsu Tanaka, Y. Murakami, 2007 .

New Magnetic Nanodot Memory with FePt Nanodots

M. Koyanagi, M. Oogane, Tetsu Tanaka, 2007 .

Magnetic properties of FePt nanodots formed by a self-assembled nanodot deposition method

M. Koyanagi, M. Nishijima, Tetsu Tanaka, 2006 .

Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip

M. Koyanagi, K. Lee, T. Fukushima, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Study for CMOS device characteristics affected by ultra thin wafer thinning

M. Koyanagi, Kang-wook Lee, T. Tanaka, 2012, 2012 2nd IEEE CPMT Symposium Japan.

Chip-level TSV Process for Development of 3D System LSIs

Futoshi Furuta, Kazuyuki Hozawa, Kenichi Takeda, 2013 .

Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT

M. Koyanagi, S. Yokoyama, S. Yamada, 1990, International Technical Digest on Electron Devices.

Analysis of GOI‐MOSFET with high‐k gate dielectric and metal gate fabricated by Ge condensation technique

M. Koyanagi, T. Fukushima, J. Bea, 2006 .

A novel doping technology for ultra-shallow junction fabrication : boron diffusion from boron-adsorbed layer by rapid thermal annealing

Mitsumasa Koyanagi, Hiroyuki Kurino, Kazuhiro Hane, 2000 .

Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

M. Koyanagi, M. Nishijima, Tetsu Tanaka, 2009 .

Memory characteristics of self-assembled tungsten nanodots dispersed in silicon nitride

M. Koyanagi, M. Nishijima, Tetsu Tanaka, 2008 .

Wafer thinning for high-density three dimensional integration _ 12-inch wafer-level 3D-LSI program at GINTI

M. Koyanagi, T. Fukushima, J. Bea, 2014, 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).

Low-Cost and Self-Formed Vertical Nanowires with Aspect Ratio >100x in Deep Si-Trenches for Future 3D-LSI/IC Applications

M. Koyanagi, M. Murugesan, H. Hashimoto, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Parasitic series resistance extraction and impact ionization current modeling for SOI MOSFETs

M. Koyanagi, S. Pidin, 1998 .

Low-Temperature and High-Step-Coverage Polyimide TSV Liner Formation by Vapor Deposition Polymerization

M. Koyanagi, Kang-wook Lee, T. Fukushima, 2013 .

Improving the barrier ability of Ti in Cu through-silicon vias through vacuum annealing

M. Koyanagi, H. Nohira, T. Fukushima, 2017 .

Low-Resistance Cu-Sn Electroplated–Evaporated Microbumps for 3D Chip Stacking

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2012, Journal of Electronic Materials.

Novel submicron MOS devices by self-aligned nitridation of silicide (Sanicide)

M. Koyanagi, S. Kishino, Y. Kubota, 1985, 1985 International Electron Devices Meeting.

Pillar-shaped stimulus electrode array for high-efficiency stimulation of fully implantable epiretinal prosthesis

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2012 .

Chlorine molecular ions measured in time-modulated inductively coupled plasma by the laser-induced fluorescence technique

M. Koyanagi, K. Hane, S. Kumagai, 2001 .

Mitigation of accumulated electric charge by deposited fluorocarbon film during SiO2 etching

M. Koyanagi, Yuya Suzuki, K. Hane, 2004 .

Electrical conductivity of sidewall-deposited fluorocarbon polymer in SiO2 etching processes

M. Koyanagi, K. Hane, S. Samukawa, 2002 .

Short Channel MOS FET's Fabricated by Self-Aligned Ion Implantation and Laser Annealing

M. Koyanagi, H. Tamura, M. Miyao, 1979 .

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

Kang-Wook Lee, A Noriki, K Kiyoyama, 2011, IEEE Transactions on Electron Devices.

Optically coupled three-dimensional memory system

Mitsumasa Koyanagi, M. Koyanagi, 1991 .

Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system

Mitsumasa Koyanagi, Hiroki Mori, Hirokazu Takata, 1990 .

Electromagnetic shielding efficiency of plasma treated and electroless metal plated polypropylene nonwoven fabrics

M. Koyanagi, M. Kando, H. Matsuo, 2004 .

Capacitance characteristics of low-k low-cost CVD grown polyimide liner for high-density Cu through-Si-via in three-dimensional LSI

M. Koyanagi, T. Fukushima, J. Bea, 2016 .

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications

Mitsu Koyanagi, Takafumi Fukushima, Yangyang Yan, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Improved C-V, I–V characteristics for co-polymerized organic liner in the Through-Silicon-Via for high frequency applications by post heat treatment

M. Koyanagi, T. Fukushima, J. Bea, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Highly beneficial organic liner with extremely low Thermal stress for fine Cu-TSV in 3D-integration

M. Koyanagi, T. Fukushima, J. Bea, 2014, 2014 IEEE International Electron Devices Meeting.

Mechanical Characteristics of Thin Die/Wafers in Three-Dimensional Large-Scale Integrated Systems

M. Koyanagi, Kang-wook Lee, T. Fukushima, 2014, IEEE Transactions on Semiconductor Manufacturing.

Heterogeneous 3D integration — Technology enabler toward future super-chip

Mitsumasa Koyanagi, M. Koyanagi, 2013, 2013 IEEE International Electron Devices Meeting.

Non-conductive film underfill for 3D integration of 20 pm-thick LSI wafers with fine Cu-TSVs

M. Koyanagi, T. Fukushima, J. Bea, 2016, 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study

Tetsu Tanaka, Takafumi Fukushima, K. W. Lee, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Revisiting the silicon-lattice in the high-density 3D-LSIs — In the perspective of device reliability

M. Koyanagi, T. Fukushima, J. Bea, 2013, 2013 IEEE International Electron Devices Meeting.

Three-dimensional shared memory fabricated using wafer stacking technology

K. W. Lee, T. Ono, Tomokatsu Mizukusa, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Locally induced stress in stacked ultrathin Si wafers: XPS and μ-Raman study

M. Koyanagi, H. Nohira, T. Fukushima, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Replacing the PECVD-SiO2 in the through-silicon via of high-density 3D LSIs with highly scalable low cost organic liner: Merits and demerits

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Mechanical characteristics of thin dies/wafers in three-dimensional large-scale integrated systems

M. Koyanagi, T. Fukushima, J. Bea, 2013, ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference.

Cu lateral interconnects formed between 100-µm-thick self-assembled chips on flexible substrates

M. Koyanagi, K. Kiyoyama, H. Kino, 2009, 2009 59th Electronic Components and Technology Conference.

High-Density Through Silicon Vias for 3-D LSIs

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2009, Proceedings of the IEEE.

Stress-induced double-hump substrate current in MOSFET's

M. Koyanagi, A. Lewis, J. Shaw, 1986, IEEE Electron Device Letters.

Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems

M. Koyanagi, T. Fukushima, Daisaku Matsukawa, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

Mitsumasa Koyanagi, Kang Wook Lee, Tetsu Tanaka, 2016, Micromachines.

Damage To Gate Oxides In Reactive Ion Etching

M. Koyanagi, T. Y. Huang, I.-W. Wu, 1990, Other Conferences.

500 nm-sized Ni-TSVwith Aspect Ratio 20 for Future 3D-LSIs_A Low-Cost Electroless-Ni Plating Approach

M. Koyanagi, T. Fukushima, M. Murugesan, 2019, 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal

Takafumi Fukushima, Mariappan Murugesan, H. Hashimoto, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

High-resolution long-array thermal ink jet printhead fabricated by anisotropic wet etching and deep Si RIE

M. Koyanagi, M. Fujii, M. Koyanagi, 2004, Journal of Microelectromechanical Systems.

New Electrically Thinned Intrinsic-Channel SOI MOSFET with 0.01 µm Channel Length

M. Koyanagi, S. Pidin, T. Shimatani, 1997 .

SiGe elevated source/drain structure and nickel silicide contact layer for sub 0.1 μm MOSFET fabrication

Mitsumasa Koyanagi, Hiroyuki Kurino, Hoon Choi, 2004 .

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding

Mitsumasa Koyanagi, Kang Wook Lee, Tetsu Tanaka, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack

Mitsumasa Koyanagi, Kang Wook Lee, Katsuyuki Sakuma, 2009, 2009 IEEE International Conference on 3D System Integration.

Two-Dimensional Device Simulation for Polycrystalline Silicon Thin-Film Transistor

M. Koyanagi, S. Yokoyama, S. Yamada, 1990 .

A closed-loop power control function for bio-implantable devices

M. Koyanagi, Y. Tanaka, K. Kiyoyama, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

Perfect conformal deposition of electroless Cu for high aspect ratio through-Si Vias

Mitsumasa Koyanagi, Takafumi Fukushima, Kazuhiro Yamamoto, 2009 .

A new two‐dimensional analysis method for polycrystalline‐silicon tfts

M. Koyanagi, S. Yamada, N. Kato, 1993 .

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Power Supply System Using Electromagnetic Induction for Three-Dimensionally Stacked Retinal Prosthesis Chip

Mitsumasa Koyanagi, Hiroyuki Kurino, Takafumi Fukushima, 2008 .

Evaluation of Platinum-Black Stimulus Electrode Array for Electrical Stimulation of Retinal Cells in Retinal Prosthesis System

Mitsumasa Koyanagi, Hiroyuki Kurino, Takafumi Fukushima, 2007 .

The charge-pumping technique for grain boundary trap evaluation in polysilicon TFTs

M. Koyanagi, I.-W. Wu, M. Koyanagi, 1992, IEEE Electron Device Letters.

Novel Optical/Electrical Printed Circuit Board with Polynorbornene Optical Waveguide

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2007 .

Characteristics of Copper Spiral Inductors Utilizing FePt Nanodot Films

Mitsumasa Koyanagi, Takafumi Fukushima, Akihiro Noriki, 2009 .

Development of Si Double-Sided Microelectrode for Platform of Brain Signal Processing System

Tetsu Tanaka, M. Koyanagi, Hajime Mushiake, 2008 .

Handbook of 3D Integration

Mitsumasa Koyanagi, Peter Ramm, Philip Garrou, 2008 .

Recent progress in 3D integration technology

Mitsumasa Koyanagi, M. Koyanagi, 2015, IEICE Electron. Express.

Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides

M. Koyanagi, T. Fukushima, Yuka Ito, 2012 .

Optical Interposer Technology using Buried Vertical-Cavity Surface-Emitting Laser Chip and Tapered Through-Silicon Via for High-Speed Chip-to-Chip Optical Interconnection

Mitsumasa Koyanagi, Takafumi Fukushima, Akihiro Noriki, 2009 .

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

M. Koyanagi, M. Koyanagi, Kang-wook Lee, 2011, IEEE Electron Device Letters.

Cell characteristics of a multiple alloy nano-dots memory structure

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2009 .

Proposal of New Nonvolatile Memory with Magnetic Nano-Dots

M. Koyanagi, H. Kurino, H. Choi, 2004 .

Low-temperature oriented growth in [CoPt/MgO]n multi-layer

M. Koyanagi, M. Kurosawa, M. Miyao, 2008 .

New Magnetic Flash Memory with FePt Magnetic Floating Gate

M. Koyanagi, K. Natori, M. Miyao, 2006 .

New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

H. Kikuchi, M. Koyanagi, T. Tanaka, 2007, 2007 IEEE International Electron Devices Meeting.

Effects of Ion Implantation Damage on Elevated Source/Drain Formation for Ultrathin Body Silicon on Insulator Metal Oxide Semiconductor Field-Effect Transistor

M. Koyanagi, T. Fukushima, T. Sakaguchi, 2006 .

Relationships between the diversity of the opsins and that of photoreceptive systems

M. Koyanagi, 2008 .

New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

Mitsumasa Koyanagi, Takafumi Fukushima, M. Koyanagi, 2005 .

Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing

M. Koyanagi, Tetsu Tanaka, T. Fukushima, 2021, 2021 IEEE International 3D Systems Integration Conference (3DIC).

Chip-to-Chip Hybrid Bonding with Larger-Oriented Cu Grains for µ-joints Beyond 100 K

M. Koyanagi, T. Fukushima, T. Miyazaki, 2023, 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).

Nano Ni/Cu-TSVs with an Improved Reliability for 3D-IC Integration Application

M. Koyanagi, T. Fukushima, J. Bea, 2020, 2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Tight-Pitched 10 μm-Width Solder Joints for c-2-c and c-2-w 3D-Integration in NCF Environment

M. Koyanagi, T. Fukushima, J. Bea, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Tight-Pitch Au-Sn Interconnections for 3D-ICs Integration and Packaging Applications

M. Koyanagi, T. Fukushima, M. Mariappan, 2020, Electronic Components and Technology Conference.

Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

M. Koyanagi, R.A. Martin, M. Koyanagi, 1987, IEEE Transactions on Electron Devices.

Neuromorphic vision chip fabricated using three-dimensional integration technology

Ki-Tae Park, M. Koyanagi, T. Nakamura, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Mitsumasa Koyanagi, Takafumi Fukushima, Hisashi Kino, 2016, Journal of Microelectromechanical Systems.

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature

Mitsumasa Koyanagi, Kang Wook Lee, Tetsu Tanaka, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Future system-on-silicon LSI chips

Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, 1998, IEEE Micro.

Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme with Selective Word Line Bootstrap

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2007 .

A novel atomic layer doping technology for ultra-shallow junction in sub-0.1 /spl mu/m MOSFETs

M. Koyanagi, H. Kurino, K. Kato, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration

Mitsumasa Koyanagi, Kang Wook Lee, Tetsu Tanaka, 2014, 2014 International 3D Systems Integration Conference (3DIC).

Intelligent image sensor chip with three dimensional structure

T. Nakamura, H. Kurino, K.W. Lee, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Challenges in 3D Integration

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2018 .

Performances and physical mechanisms in sub-0.1 µm gate length LDD MOSFETs at low temperature

M. Koyanagi, F. Balestra, T. Matsumoto, 1994 .

Optical waveguides on silicon chips

M. Koyanagi, S. Miyazaki, M. Hirose, 1995 .

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface

Hong Ding, Manabu Sato, Takeshi Ogawa, 2012, 2012 IEEE International Solid-State Circuits Conference.

Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2010, IEEE Custom Integrated Circuits Conference 2010.

Novel Retinal Prosthesis System with Three Dimensionally Stacked LSI Chip

M. Koyanagi, H. Kurino, T. Watanabe, 2006, 2006 European Solid-State Device Research Conference.

Reconfigurable Parallel Image Processing System Using Three-Dimensional LSI

M. Koyanagi, Tetsu Tanaka, T. Sugimura, 2006 .

A new LDD transistor with inverse-T gate structure

M. Koyanagi, R.A. Martin, M. Koyanagi, 1987, IEEE Electron Device Letters.

Investigation and reduction of hot electron induced punchthrough (HEIP) effect in submicron PMOSFETs

M. Koyanagi, R.A. Martin, M. Koyanagi, 1986, 1986 International Electron Devices Meeting.

A novel submicron LDD transistor with inverse-T gate structure

M. Koyanagi, R.A. Martin, M. Koyanagi, 1986, International Electron Devices Meeting.

Connectivity in Electronic Packaging

Tadahiro Kuroda, Hiroki Ishikuro, Mitsumasa Koyanagi, 2018, VLSI Design and Test for Systems Dependability.

Yield enhancement and mitigating the Si-chipping and wafer cracking in ultra-thin 20µm-thick 8- and 12-inch LSI wafer

M. Koyanagi, T. Fukushima, J. Bea, 2015, 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI

Tetsu Tanaka, S. Kimura, Takafumi Fukushima, 2014, 2014 International 3D Systems Integration Conference (3DIC).

Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

M. Koyanagi, Kang-wook Lee, Tetsu Tanaka, 2014, IEEE Transactions on Electron Devices.

Development of via-last 3D integration technologies using a new temporary adhesive system

Mitsumasa Koyanagi, Kang Wook Lee, Takafumi Fukushima, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV

H. Wang, Mitsumasa Koyanagi, Kang Wook Lee, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

High density Cu-TSVs and reliability issues

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs

M. Koyanagi, M. Koyanagi, T. Fukushima, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Impact of Cu diffusion from Cu through-silicon via (TSV) on device reliability in 3-D LSIs evaluated by transient capacitance measurement

M. Koyanagi, Y. Ohara, M. Koyanagi, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Handbook of 3D Integration

M. Koyanagi, Philip Garrou, Peter Ramm, 2008 .

Fully-Filled, Highly-Reliable Fine-Pitch Interposers with TSV Aspect Ratio >10 for Future 3D-LSI/IC Packaging

Mitsumasa Koyanagi, Takafumi Fukushima, Makoto Motoyoshi, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

New multichip-to-wafer 3D integration technology using Self-Assembly and Cu nano-pillar hybrid bonding

M. Koyanagi, K. Lee, T. Fukushima, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Impact of Electroless-Ni Seed Layer on Cu-Bottom-up Electroplating in High Aspect Ratio (>10) TSVs for 3D-IC Packaging Applications

M. Koyanagi, T. Fukushima, M. Mariappan, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

A Fundamental Study Toward the Realization of an SPRAM-based Low Power FPGA

M. Koyanagi, Tetsu Tanaka, K. Kiyoyama, 2008 .

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2014, 2014 IEEE International Reliability Physics Symposium.

High Performance Polynorbornene Optical Waveguide for Opto-Electric Interconnections

M. Koyanagi, K. Watanabe, Y. Shirato, 2007, Polytronic 2007 - 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics.

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

M. Koyanagi, H. Naganuma, T. Tani, 2012, IEEE Electron Device Letters.