K. Asano

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

C. Hu, D. Hisamoto, Wen-Chin Lee, 2000 .

Ultra-thin body SOI MOSFET for deep-sub-tenth micron era

Chenming Hu, Tsu-Jae King, N. Lindert, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Chenming Hu, Tsu-Jae King, N. Lindert, 2000, IEEE Electron Device Letters.

Sub-50 nm P-channel FinFET

C. Hu, D. Hisamoto, Wen-Chin Lee, 2001 .

Sub 50-nm FinFET: PMOS

Chenming Hu, Tsu-Jae King, Xuejue Huang, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A folded-channel MOSFET for deep-sub-tenth micron era

Chenming Hu, Tsu-Jae King, D. Hisamoto, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Sub-50nm FinFET : PMOS

Vivek Subramanian, Jeffrey Bokor, Chenming Hu, 1999 .

Patterning sub-30-nm MOSFET gate with i-line lithography

Chenming Hu, Tsu-Jae King, K. Asano, 2001 .

Polybenzimidazole as a thermally stable Langmuir–Blodgett film insulator in InP metal‐insulator‐semiconductor devices

K. Asano, T. Itoh, Masayoshi Suzuki, 1987 .

Long-wavelength PINFET receiver OEIC on a GaAs-on-InP heterostructure

Sadao Fujita, T. Terakado, Toshitaka Torikai, 1987 .