E. Anderson

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

C. Hu, D. Hisamoto, Wen-Chin Lee, 2000 .

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

Chenming Hu, Tsu-Jae King, N. Lindert, 2001, IEEE Electron Device Letters.

Sub-50 nm P-channel FinFET

C. Hu, D. Hisamoto, Wen-Chin Lee, 2001 .

Sub 50-nm FinFET: PMOS

Chenming Hu, Tsu-Jae King, Xuejue Huang, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A folded-channel MOSFET for deep-sub-tenth micron era

Chenming Hu, Tsu-Jae King, D. Hisamoto, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime

C. Hu, J. Kedzierski, E. Anderson, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Sub-50nm FinFET : PMOS

Vivek Subramanian, Jeffrey Bokor, Chenming Hu, 1999 .

Novel method for silicon quantum wire transistor fabrication

Jeffrey Bokor, Erik H. Anderson, J. Kedzierski, 1999 .

Sub-20 nm CMOS FinFET technologies

Chenming Hu, N. Lindert, Tsu-Jae King, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

C. Hu, J. Kedzierski, E. Anderson, 2000 .