B. Rainey

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Kok Wai Wong, E. Nowak, D. Boyd, 2002, Digest. International Electron Devices Meeting,.

Ultralow-power SRAM technology

Terence B. Hook, Atsushi Moriwaki, Matthew J. Breitwisch, 2003, IBM J. Res. Dev..

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

E. Nowak, D. Boyd, J. Kedzierski, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 0.13 m BiCMOS technology featuring a 200/280 GHz (fT/fmax) SiGe HBT

S. Jeng, B. Rainey, J. Rieh, 2003 .

A functional FinFET-DGCMOS SRAM cell

J. Kedzierski, M. Breitwisch, M. Breitwisch, 2002, Digest. International Electron Devices Meeting,.

Demonstration of FinFET CMOS circuits

J. Kedzierski, E. Nowak, J. Kedzierski, 2002, 60th DRC. Conference Digest Device Research Conference.

A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications

David Harame, Richard A. Phelps, Yun Shi, 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

Scaling beyond the 65 nm node with FinFET-DGCMOS

Joachim Keinert, David M. Fried, Matthew J. Breitwisch, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Improved vertical PNP collector-base breakdown using 2D Monte-Carlo TCAD simulations

B. Rainey, A. Stricker, N. Feilchenfeld, 2005, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005..