D. Fried

发表

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Kok Wai Wong, E. Nowak, D. Boyd, 2002, Digest. International Electron Devices Meeting,.

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

S. Narasimha, K. Onishi, J. Johnson, 2012, 2012 International Electron Devices Meeting.

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

E. Nowak, D. Boyd, J. Kedzierski, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Hybrid-orientation technology (HOT): opportunities and challenges

A. Chou, L. Shi, D. Fried, 2006, IEEE Transactions on Electron Devices.

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

D. Greenlaw, H.-J. Engelmann, N. Kepler, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Electroless Cobalt Via Pre-Fill Process for Advanced BEOL Metallization and Via Resistance Variation Reduction

D. Fried, M. Kamon, J. Gu, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Electroless Cobalt Via Pre-Fill Process for Advanced BEOL Metallization and Via Resistance Variation Reduction

D. Fried, M. Kamon, J. Gu, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

High-performance p-type independent-gate FinFETs

D. Fried, K. Kornegay, J. Duster, 2004, IEEE Electron Device Letters.

A Fin-type independent-double-gate NFET

J. Kedzierski, E. Nowak, J. Kedzierski, 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

A sub 40-nm body thickness n-type FinFET

A.P. Johnson, E. Nowak, D. Fried, 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

A functional FinFET-DGCMOS SRAM cell

J. Kedzierski, M. Breitwisch, M. Breitwisch, 2002, Digest. International Electron Devices Meeting,.

Demonstration of FinFET CMOS circuits

J. Kedzierski, E. Nowak, J. Kedzierski, 2002, 60th DRC. Conference Digest Device Research Conference.

The Design, Fabrication and Characterization of Independent-Gate FinFETs

David M. Fried, D. Fried, 2004 .

THE DESIGN, FABRICATION AND CHARACTERIZATION OF

David M. Fried, D. Fried, 2004 .

Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes

Steven E. Steen, Sharee J. McNab, Lidija Sekaric, 2006 .

Improved independent gate N-type FinFET fabrication and characterization

D. Fried, K. Kornegay, J. Duster, 2003, IEEE Electron Device Letters.

Virtual fabrication using directed self-assembly for process optimization in a 14-nm dynamic random access memory

Mattan Kamon, David M. Fried, Ken Greiner, 2016 .

Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM

Mattan Kamon, David M. Fried, Vasanth Allampalli, 2016, SPIE Advanced Lithography.

Stable SRAM cell design for the 32 nm node and beyond

Anna W. Topol, R.H. Dennard, J.W. Sleight, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization

Asen Asenov, Andrew R. Brown, Binjie Cheng, 2015, IEEE Transactions on Electron Devices.

Scaling beyond the 65 nm node with FinFET-DGCMOS

Joachim Keinert, David M. Fried, Matthew J. Breitwisch, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Extension and source/drain design for high-performance FinFET devices

Ying Zhang, David M. Fried, Meikei Ieong, 2003 .

Investigations on contact punch-through in 28 nm FDSOI through virtual fabrication

D. Fried, J. Giraudin, P. Morin, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

Chun-Yung Sung, Meikei Ieong, T. Kanarsky, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Dual stress liner enhancement in hybrid orientation technology

M. Ieong, T. Kanarsky, D. Chidambarrao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..